Memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9780144-B2
Application number	US-201615342497-A
Country	US
Kind code	B2
Filing date	Nov 3, 2016
Priority date	Feb 22, 2016
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.

First claim

What is claimed is:

1. A memory device comprising:
a plurality of first word lines extending in a first direction parallel to a top of a substrate;
a plurality of bit lines extending in a second direction, the second direction being different from the first direction;
a plurality of memory units respectively arranged at cross points between the plurality of bit lines and the plurality of first word lines, each of the plurality of memory units including a selection device, a middle electrode, and a variable resistance layer; and
a first capping layer disposed on a side wall of a recessed portion of each of the variable resistance layers and a second capping layer disposed on a side wall of a recessed portion of each of the selection devices, wherein the second capping layer is spaced apart from the first capping layer.

2. The memory device of claim 1 , wherein a first width of the middle electrode in a first direction is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction.

3. The memory device of claim 1 , wherein a side wall of the middle electrode is substantially aligned with a side wall of the first capping layer or a side wall of the second capping layer.

4. The memory device of claim 1 , further comprising:
an insulation pattern between two adjacent memory units among the plurality of memory units, the insulation pattern including a material having a dielectric constant less than a dielectric constant of the plurality of capping layers.

5. The memory device of claim 4 , wherein the insulation pattern is on a side wall of each of the plurality of capping layers and does not contact the variable resistance layer or the selection device.

6. The memory device of claim 1 , wherein
the selection device has ovonic threshold switching (OTS) characteristic, and
the selection device comprises at least two of silicon (Si), germanium (Ge), antimony (Sb), tellurium (Te), selenium (Se), indium (In), or tin (Sn), based on arsenic (As), or
the selection device comprises at least two of silicon (Si), germanium (Ge), antimony (Sb), tellurium (Te), arsenic (As), indium (In), or tin (Sn), based on selenium (Se).

7. The memory device of claim 1 , further comprising:
a driving circuit area between the top of the substrate and a bottom of each of the plurality of first word lines or between the top of the substrate and a bottom of each of the plurality of bit lines, the driving circuit area including a plurality of driving circuits configured to drive the plurality of memory units.

8. The memory device of claim 1 , further comprising an insulation liner between the first capping layer and the variable resistance layer.

9. A memory device, comprising:
a substrate;
an insulating interlayer disposed on the substrate;
a word line disposed on the insulation interlayer;
a bottom electrode disposed on the word line;
a selection device disposed on the bottom electrode, wherein the selection device comprises a recessed side wall, and wherein a first capping layer is disposed on the recessed side wall of the selection device;
a middle electrode disposed on the selection device;
a variable resistance layer disposed on the middle electrode, wherein the variable resistance layer comprises a recessed side wall, and wherein a second capping layer is disposed on the recessed side wall of the variable resistance layer;
a top electrode disposed on the variable resistance layer; and
a bit line disposed on the top electrode.

10. The memory device of claim 9 , wherein a side wall of the middle electrode is substantially aligned with a side wall of the first capping layer and a side wall of the second capping layer.

11. The memory device of claim 10 , further comprising an insulation pattern disposed on the side walls of each of the first capping layer, the middle electrode, and the second capping layer, wherein the insulation pattern is separated from the recessed side wall of the selection device by the first capping layer, and wherein the insulation pattern is separated from the recessed side wall of the variable resistance layer by the second capping layer.

12. The memory device of claim 9 , further comprising an insulation liner between the second capping layer and the variable resistance layer.

13. The memory device of claim 9 , wherein a width of the selection device is substantially the same as a width of the variable resistance layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seong Dong-Jun
• Park Soon-Oh

Classifications

• H01L27/249

  Electricity · mapped topic

• H01L27/2427 Primary

  Electricity · mapped topic

• H10D84/01

  Manufacture or treatment · CPC title

• H10N70/063

  by etching of pre-deposited switching material layers, e.g. lithography · CPC title

• H10B63/84 Primary

  arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays · CPC title