Variable resistance memory devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9685609-B2
Application number	US-201514963947-A
Country	US
Kind code	B2
Filing date	Dec 9, 2015
Priority date	Dec 22, 2014
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A variable resistance memory device includes a plurality of first conductive lines, each of the first conductive lines extends in a first direction, a plurality of second conductive lines are above the first conductive lines, and each of the second conductive lines extend in a second direction transverse to the first direction. A plurality of first memory cells are at intersections where the first and second conductive lines overlap each other, each of the first memory cells including a first variable resistance structure having a first variable resistance pattern, a first sacrificial pattern and a second variable resistance pattern sequentially stacked in the first direction on a first plane. A plurality of third conductive lines are above the second conductive lines, each of the third conductive lines extend in the first direction, and a plurality of second memory cells are at intersections where the second and the third conductive lines overlap each other. Each of the second memory cells includes a second variable resistance structure having a third variable resistance pattern, a second sacrificial pattern and a fourth variable resistance pattern sequentially stacked in the first direction on second plane.

First claim

What is claimed is:

1. A variable resistance memory device comprising:
a plurality of first conductive lines on a substrate, each of the first conductive lines extending in a first direction;
a plurality of second conductive lines above the first conductive lines, each of the second conductive lines extending in a second direction transverse to the first direction;
a plurality of first memory cells at intersections where the first and second conductive lines overlap each other, each of the first memory cells including a first variable resistance structure having a first variable resistance pattern, a first sacrificial pattern and a second variable resistance pattern sequentially stacked in the first direction on substantially a first plane;
a plurality of third conductive lines above the second conductive lines, each of the third conductive lines extending in the first direction;
a plurality of second memory cells at intersections where the second and the third conductive lines overlap each other, each of the second memory cells including a second variable resistance structure having a third variable resistance pattern, a second sacrificial pattern and a fourth variable resistance pattern sequentially stacked in the first direction on substantially a second plane; and
a first capping pattern on first and second sidewalls facing in the first direction of each of the first and second memory cells.

2. The variable resistance memory device of claim 1 , wherein the first memory cell includes a first lower electrode, a first switching element, the first variable resistance structure and a first upper electrode sequentially stacked on the first conductive line, and the second memory cell includes a second lower electrode, a second switching element, the second variable resistance structure and a second upper electrode sequentially stacked on the second conductive line.

3. The variable resistance memory device of claim 1 , wherein the first to fourth variable resistance patterns comprise the same transition metal oxide.

4. The variable resistance memory device of claim 3 , wherein the first to fourth variable resistance patterns comprise at least one of titanium oxide (TiOx), zirconium oxide (ZrOx), aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), niobium oxide (NbOx), cobalt oxide (CoOx), tungsten oxide (WOx), lanthanum oxide (LaOx), and zinc oxide (ZnOx).

5. The variable resistance memory device of claim 3 , further comprising a first buffer pattern on the first variable resistance structure and a second buffer pattern on the second variable resistance structure, wherein the first buffer pattern absorbs oxygen from the first and second variable resistance patterns or supplies oxygen thereto, and the second buffer pattern absorbs oxygen from third and fourth variable resistance patterns or supplies oxygen thereto.

6. The variable resistance memory device of claim 1 , wherein the first capping pattern comprises the same material as a material of the first to fourth variable resistance patterns.

7. The variable resistance memory device of claim 1 , further comprising a second capping pattern and a third capping layer wherein the second capping pattern is formed on third and fourth sidewalls facing in the second direction of the first memory cell, and the third capping layer is formed on the third and fourth sidewalls facing in the second direction of the second memory cell.

8. The variable resistance memory device of claim 7 , wherein each of the second capping pattern and the third capping layer comprises a material different from a material of the first capping pattern.

9. The variable resistance memory device of claim 1 , wherein the first and second sacrificial patterns comprise an insulating material.

10. The variable resistance memory device of claim 1 , further comprising a first insulation pattern filling a gap between structures disposed in the second direction, each of the structures including the first conductive line and the first memory cell sequentially stacked in the second direction, and a second insulation pattern filling a gap between structures disposed in the first direction, each of the structures including the first memory cell, the second conductive line and the second memory cell sequentially stacked.

11. A resistance memory device comprising:
a first electrode;
a switching element on the first electrode;
a variable resistance structure on the switching element, the variable resistance structure including a first resistance pattern and a second resistance pattern which are horizontally spaced apart from each other;
a second electrode on the variable resistance structure; and
a capping layer on sidewalls of the switching element and the first and second resistance patterns; wherein the capping layer is the same material as a material of the first and second resistance patterns.

12. The variable resistance memory device of claim 11 , wherein the variable resistance structure further comprises an insulating pattern between the first resistance pattern and the second resistance pattern, and the first resistance pattern and the second resistance pattern are separated by the insulating pattern.

13. The variable resistance memory device of claim 11 , wherein the first and second resistance patterns are spaced apart from each other in a first direction, and a width in the first direction of each of the first and second resistance patterns is less than a width in a second direction transverse to the first direction.

14. The variable resistance memory device of claim 11 , wherein the first and second resistance patterns comprise one of a transition metal oxide and a perovskite-based material.

15. A variable resistance memory device comprising:
a plurality of first conductive lines on an insulation layer of a substrate, each of the first conductive lines extending in a first direction;
a plurality of second conductive lines above the first conductive lines, each of the second conductive lines extending in a second direction transverse to the first direction;
a plurality of first memory cells at intersections where the first and second conductive lines overlap each other, each of the first memory cells including a first variable resistance structure having variable resistance patterns stacked in the first direction on a first plane;
a plurality of third conductive lines above the second conductive lines, each of the third conductive lines extending in the first direction;
a plurality of second memory cells at intersections where the second and the third conductive lines overlap each other, each of the second memory cells including a second variable resistance structure having variable resistance patterns stacked in the first direction on a second plane; and
a first capping pattern on first and second sidewalls facing in the first direction of each of the first and second memory cells.

16. The variable resistance memory device of claim 15 , wherein the first memory cell includes a first lower electrode, a first switching element, the first variable resistance structure and a first upper electrode stacked on the first conductive line, and the second memory cell includes a second lower electrode, a second switching element, the second variable resistance structure and a second upper electrode stacked on the second conductive line.

17. The variable resistance memory device of claim 16 , further comprising a first buffer pattern on the first variable resistance structure and a second buffer pattern on the second variable resistance structure, wherein the

Assignees

• Jung Seung-Jae
• Kang Youn-Seon
• Samsung Electronics Co Ltd

Inventors

• Jung Seung-Jae
• Kang Youn-Seon

Classifications

• H01L45/1266

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic

• H01L27/2409

  Electricity · mapped topic

• H01L45/141

  Electricity · mapped topic

• H01L27/2481

  Electricity · mapped topic