Semiconductor device

Patent metadata

Field	Value
Publication number	US-11769726-B2
Application number	US-202217744375-A
Country	US
Kind code	B2
Filing date	May 13, 2022
Priority date	Aug 1, 2019
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

A semiconductor device includes a first gate electrode disposed on a substrate and extending in a first horizontal direction, a first gate contact and a dummy gate contact, which are spaced apart from each other in the first horizontal direction and are in contact with a top surface of the first gate electrode, a first interconnect line extending in a second horizontal direction and overlapping the first gate contact in a vertical direction with respect to the upper surface of the substrate, and a voltage generator configured to generate a first voltage and apply the first voltage to the first gate electrode via the first interconnect line and the first gate contact. The first gate electrode receives the first voltage via the first interconnect line and the first gate contact from the voltage generator. The dummy gate contact receives the first voltage via the first gate electrode.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a plurality of gate electrodes on a substrate,
wherein each of the plurality of gate electrodes extends in a first horizontal direction with respect to an upper surface of the substrate and the plurality of gate electrodes are spaced apart from each other in a second horizontal direction, with respect to the upper surface of the substrate, different from the first horizontal direction;
a plurality of gate contacts,
wherein each of the plurality of gate contacts is disposed on a respective one of the plurality of gate electrodes and electrically connected thereto;
a plurality of interconnect lines,
wherein each of the plurality of interconnect lines extends in the second horizontal direction and overlaps, in a vertical direction with respect to the upper surface of the substrate, at least one gate contact of the plurality of gate contacts, and
wherein the plurality of interconnect lines are spaced apart from each other in the first horizontal direction;
a voltage generator configured to generate a first voltage and apply the first voltage to the plurality of gate electrodes through the plurality of gate contacts and the plurality of interconnect lines; and
a dummy gate contact, which is disposed on a corresponding one gate electrode of the plurality of gate electrodes and is spaced apart, in the first horizontal direction, from a gate contact disposed on the corresponding one gate electrode,
wherein the first voltage is applied to the dummy gate contact through the corresponding one gate electrode.

2. The semiconductor device of claim 1 , further comprising:
a plurality of gate vias disposed on the plurality of gate contacts,
wherein each of the plurality of gate vias is interposed, in the vertical direction, between a respective gate contact of the plurality of gate contacts and a respective interconnect lines of the plurality of interconnect lines.

3. The semiconductor device of claim 1 , further comprising:
a dummy gate via disposed on the dummy gate contact.

4. The semiconductor device of claim 3 , further comprising:
a dummy interconnect line disposed on the dummy gate via,
wherein the dummy gate via is interposed, in the vertical direction, between the dummy interconnection line and the dummy gate contact, and
wherein the first voltage from the voltage generator is applied to the dummy interconnection line through the dummy gate contact and the dummy gate via.

5. The semiconductor device of claim 1 , further comprising:
a device isolation layer, which is disposed in the substrate to define a first active region and a second active region spaced apart from each other in the first horizontal direction,
wherein the dummy gate contact overlaps in the vertical direction or is adjacent, in the first horizontal direction, to one of the first active region and the second active region.

6. The semiconductor device of claim 5 ,
wherein the plurality of gate electrodes are disposed to cross over the first active region and the second active region,
wherein at least one of the plurality of gate contacts is disposed between the first active region and the second active region and on the device isolation layer, and
wherein the dummy gate contact overlaps in the vertical direction or is adjacent, in the first horizontal direction, to one of the first active region and the second active region.

7. The semiconductor device of claim 5 , further comprising:
an active fin, which protrudes from the substrate in the vertical direction and has a top surface higher than a top surface of the device isolation layer,
wherein the dummy gate contact overlaps the active fin.

8. A semiconductor device, comprising:
a substrate including a first active region and a second active region, which are spaced apart from each other in a first horizontal direction with respect to an upper surface of the substrate;
a first gate electrode crossing the first active region and extends in the first horizontal direction;
a second gate electrode crossing the second active region and extends in the first horizontal direction;
a gate separation pattern interposed between the first gate electrode and the second gate electrode;
a first gate contact in contact with a top surface of the first gate electrode; and
a first dummy gate contact in contact with a top surface of the second gate electrode,
wherein a first voltage is applied to the first gate contact and no voltage is applied to the first dummy gate contact.

9. The semiconductor device of claim 8 , wherein the first and second gate electrodes located on a single straight line extending in the first horizontal direction.

10. The semiconductor device of claim 8 , further comprising:
a gate via disposed on the first gate contact; and
a first interconnection line on the gate via.

11. The semiconductor device of claim 8 , further comprising:
a device isolation layer, which is disposed in the substrate to define the first active region and the second active region,
wherein the first gate contact overlaps the device isolation layer, and the first dummy gate contact overlaps the second active region.

12. The semiconductor device of claim 8 , further comprising:
a third gate electrode which is spaced apart from the first gate electrode in a second horizontal direction with respect to an upper surface of the substrate and extends in the first horizontal direction;
a second gate contact disposed on the third gate electrode; and
a second dummy gate contact spaced apart from the second gate contact and disposed on the third gate electrode.

13. The semiconductor device of claim 12 , wherein a second voltage is applied to the second gate contact and the second dummy gate contact receives the second voltage through the third gate electrode.

14. The semiconductor device of claim 12 , further comprising:
a second gate via disposed on the second gate contact; and
a second interconnection line disposed on the second gate via.

15. A semiconductor device, comprising:
a substrate including a first active region and a second active region, which are spaced apart from each other in a first horizontal direction with respect to an upper surface of the substrate;
a device isolation layer disposed in the substrate and defining the first and second active regions;
a first active fin and a second active fin which protrude from the substrate in a vertical direction and disposed on the first and second active regions, respectively;
a gate electrode crossing the first and second active fins in the first horizontal direction;
a plurality of first channel patterns stacked in the vertical direction on each other on the first active fin;
a plurality of second channel patterns stacked in the vertical direction on each other on the second active fin;
a gate contact in contact with a top surface of the gate electrode; and
a dummy gate contact spaced apart from the gate contact and in contact with the top surface of the gate electrode,
wherein the gate electrode is configured to surround each of the plurality of first and second channel patterns, and
wherein the gate contact overlaps the device isolation layer and the dummy gate contact overlaps the first active fin.

16. The semiconductor device of claim 15 , further comprising:
a gate insulating layer between the gate electrode and the plurality of first and second channel patterns, wherein the gate insulating layer surrounds each of the plurality of first and second channel patterns.

17. The semiconductor device of cl

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Byounggon
• Kim Changbeom
• Lee Dalhee
• Choi Eun-Hee

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title