Semiconductor device layout having a power rail

Patent metadata

Field	Value
Publication number	US-9865544-B2
Application number	US-201514874916-A
Country	US
Kind code	B2
Filing date	Oct 5, 2015
Priority date	Oct 5, 2015
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

A semiconductor device is provided as follows. An active region extends along a first direction. A gate line overlaps the active region and extending along a second direction intersecting the first direction. A power rail has a main pattern extending along the first direction and a sub-pattern branching off from the main pattern to extend along the second direction. A first source/drain contact, electrically connected to the power rail, overlaps the active region and the sub-pattern.

First claim

What is claimed is:

1. A semiconductor device comprising:
an active region extending along a first direction;
a gate line overlapping the active region and extending along a second direction intersecting the first direction;
a power rail having a main pattern extending along the first direction and a sub-pattern branching off from the main pattern to extend along the second direction; and
a first source/drain contact overlapping the active region, the main pattern and the sub-pattern,
wherein the first source/drain contact is electrically connected to the power rail,
wherein the sub-pattern overlaps the gate line, and
wherein the first source/drain contact does not overlap the gate line.

2. The semiconductor device of claim 1 , further comprising
a second source/drain contact disposed on the active region,
wherein the second source/drain contact does not overlap the main pattern and the sub-pattern.

3. The semiconductor device of claim 1 ,
wherein the power rail and the first source/drain contact are disposed in a first level layer.

4. The semiconductor device of claim 1 ,
wherein the first source/drain contact further overlaps the main pattern.

5. The semiconductor device of claim 1 ,
wherein the power rail and the first source/drain contact are disposed in a same level layer.

6. The semiconductor device of claim 1 , further comprising
a metal interconnect disposed on the first source/drain contact, vertically overlapped the first source/drain contact in a third direction intersecting the first and second direction, and the metal interconnect is spaced apart from the first source/drain contact in the third direction.

7. The semiconductor device of claim 3 ,
wherein an upper surface of the power rail and an upper surface of the first source/drain contact are coplanar.

8. The semiconductor device of claim 6 ,
wherein the metal interconnect overlaps the active region and is disposed adjacent to the power rail.

9. A semiconductor device comprising:
an active region extending along a first direction;
a gate line overlapping the active region and extending along a second direction intersecting the first direction;
a power rail having a main pattern extending along the first direction and a recessed region recessed from the main pattern; and
a first source/drain contact overlapping the active region and the main pattern,
wherein the first source/drain contact is electrically connected to the power rail,
wherein the power rail and the first source/drain contact are disposed in a same level layer,
wherein the recessed region is spaced apart from the first source/drain contact, and
wherein a bottom surface of the power rail is coplanar with a bottom surface of the first source/drain contact.

10. The semiconductor device of claim 9 , further comprising
a second source/drain contact disposed at a location surrounded by the recessed region and the main pattern.

11. The semiconductor device of claim 9 , further comprising
a metal interconnect disposed on the first source/drain contact, vertically overlapped the first source/drain in a third direction intersecting the first and second direction, and spaced apart from the first source/drain contact in the third direction,
wherein the power rail is connected to a ground voltage.

12. The semiconductor device of claim 10 ,
wherein the first and second source/drain contacts do not overlap the gate line.

13. A semiconductor device having multilevel layers, comprising:
a first level layer having an active region;
a second level layer having a first source/drain contact and a power rail, wherein the power rail includes a main pattern and a sub-pattern protruding from the main pattern, wherein an upper surface of the first source/drain contact is coplanar with an upper surface of the power rail; and
a third level layer having a metal interconnect,
wherein the metal interconnect overlaps the active region and the first source/drain contact when viewed from the above of the semiconductor device,
wherein the third level layer is higher than the first level layer and the second level layer, and
wherein the second level layer is higher than the first level layer.

14. The semiconductor device of claim 13 , further comprising a fourth level layer having a via disposed on the power rail,
wherein the fourth level layer is interposed between the second level layer and the third level layer.

15. The semiconductor device of claim 13 ,
wherein the power rail is in contact with the first source/drain contact.

16. The semiconductor device of claim 13 , further comprises:
a second source/drain contact disposed on the metal interconnect,
wherein the second source/drain contact is connected electrically to the metal interconnect, and
wherein the first source/drain contact is isolated from the metal interconnect by an insulation layer interposed between the metal interconnect and the first source/drain contact.

17. The semiconductor device of claim 13 ,
wherein the first level layer, the second level layer and the third level layer are stacked perpendicular to the active region.

18. The semiconductor device of claim 15 ,
wherein the via overlaps the main pattern and the first source/drain contact when viewed from the above of the semiconductor device.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Jong-Hoon

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/427 Primary

  Power or ground buses · CPC title

• H01L23/5226

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic