Metal-based etch-stop layer

Patent metadata

Field	Value
Publication number	US-11769693-B2
Application number	US-202117316063-A
Country	US
Kind code	B2
Filing date	May 10, 2021
Priority date	Apr 27, 2018
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

A semiconductor structure includes a conductive feature, a first metal-based etch-stop layer over the underlying structure, a metal-free etch-stop layer over the first metal-based etch-stop layer, a second metal-based etch-stop layer over the metal-free etch-stop layer, an interlayer dielectric layer over the second metal-based etch-stop layer, and an interconnect structure extending through the first metal-based etch-stop layer, metal-free etch-stop layer, and the second metal-based etch-stop layer, wherein a bottom portion of the conductive interconnect structure directly contacts the conductive feature. The first metal-based etch-stop layer may include a first metallic component having one of aluminum, tantalum, titanium, or hafnium, and the second metal-based etch-stop layer may include a second metallic component the same as or different from the first metallic component. The first metal-based etch-stop layer and the second metal-based etch-stop layer may both be free of silicon.

First claim

What is claimed is:

1. A device comprising:
a first conductive feature;
a first etch stop layer that includes a first metallic component disposed over the first conductive feature;
a second etch stop layer that includes a second metallic component that is different than the first metallic component, the second etch stop layer disposed over the first etch stop layer; and
a metal-free etch stop layer disposed over the first etch stop layer; and
a conductive material extending through the first etch stop layer, the second etch stop layer and the metal-free etch stop layer.

2. The device of claim 1 , wherein the first etch stop layer is substantially free of silicon.

3. The device of claim 1 , wherein the first etch stop layer and the second etch stop layer are substantially free of silicon.

4. The device of claim 1 , wherein the metal-free etch stop layer is disposed between the first etch stop layer and the second etch stop layer.

5. The device of claim 1 , wherein the first metallic component is part of a first metal based dielectric material, the first metal based dielectric material selected from the group consisting of a metal oxide, a metal nitride, a metal carbide and a metal oxynitride, and
wherein the second metallic component is part of a second metal based dielectric material, the second metal based dielectric material selected from the group consisting of a metal oxide, a metal nitride, a metal carbide and a metal oxynitride.

6. The device of claim 1 , wherein the metal-free etch stop layer includes a material selected from the group consisting of silicon oxide, silicon nitride, silicon carbide and silicon oxynitride.

7. The device of claim 1 , wherein the first conductive feature includes a source/drain region.

8. A device comprising:
a first etch stop layer that includes a first metallic component disposed over a substrate;
a second etch stop layer that includes a second metallic component that is different than the first metallic component, the second etch stop layer disposed over the first etch stop layer; and
a metal-free etch stop layer having a thickness about 1.5 times a thickness of either the first etch stop layer or the second dielectric layer, the metal-free etch stop layer disposed over the first etch stop layer; and
a conductive material extending through the first dielectric layer, the second dielectric layer and the metal-free etch stop layer.

9. The device of claim 8 , wherein the first etch stop layer is disposed under the metal-free etch stop layer and the second etch stop layer is disposed over the metal-free etch stop layer.

10. The device of claim 8 , wherein the metal-free etch stop layer interfaces with both the first etch stop layer and the second etch stop layer.

11. The device of claim 8 , further comprising:
a gate structure disposed over a substrate;
a source/drain feature associated with the gate structure and disposed on the substrate, and
wherein the conductive material extend is electrically coupled to the source/drain feature.

12. The device of claim 8 , wherein the first metallic component includes a material selected from the group consisting of aluminum (Al), tantalum (Ta), titanium (Ti), hafnium (Hf), molybdenum (Mo), silver (Ag), gold (Au), manganese (Mn) and zirconium (Zr), and
wherein the second metallic component includes a material selected from the group consisting of aluminum (Al), tantalum (Ta), titanium (Ti), hafnium (Hf), molybdenum (Mo), silver (Ag), gold (Au), manganese (Mn) and zirconium (Zr).

13. The device of claim 8 , wherein the first metallic component is part of a first metal based dielectric material, the first metal based dielectric material selected from the group consisting of a metal oxide, a metal nitride, a metal carbide and a metal oxynitride, and
wherein the second metallic component is part of a second metal based dielectric material, the second metal based dielectric material selected from the group consisting of a metal oxide, a metal nitride, a metal carbide and a metal oxynitride, and
wherein the metal-free etch stop layer includes a material selected from the group consisting of silicon oxide, silicon nitride, silicon carbide and silicon oxynitride.

14. The device of claim 8 , wherein the first etch stop layer and the second etch stop layer are substantially free of silicon, and
wherein the metal-free etch stop layer includes silicon.

15. A method comprising:
forming a first etch-stop layer over a conductive structure, the first etch-stop layer including a first metal component;
forming a metal-free etch-stop layer on the first dielectric etch-stop layer; and
forming a second etch-stop layer on the non-meal etch-stop layer, the second etch-stop layer including a second metal component that is different than the first metal component.

16. The method of claim 15 , wherein the metal-free etch-stop layer has a thickness about 1.5 times a thickness of either the first etch stop layer or the second etch stop layer after the forming of the second etch-stop layer on the metal-free etch-stop layer.

17. The method of claim 15 , further comprising forming a trench extending through the first etch-stop layer, the metal-free etch-stop layer and the second etch-stop layer, wherein the forming of the trench includes performing different etching processes on the first etch-stop layer and the metal-free etch-stop layer.

18. The method of claim 15 , wherein the forming of the trench extending through the first etch-stop layer, the metal-free etch-stop layer and the second etch-stop layer includes:
performing a first etching process with a first etchant to etch a portion of the second etch-stop layer;
performing a second etching process with a second etchant to etch a portion of the metal-free etch-stop layer, the second etchant being different than the first etchant; and
performing a third etching process to etch with a third etchant to etch a portion of the first etch-stop layer.

19. The method of claim 18 , wherein the third etchant is formed of the same material as the first etchant.

20. The device of claim 1 , wherein the metal-free etch stop layer interfaces with one of the first etch stop layer and the second etch stop layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tung Szu-Ping
• Lin Yu-Kai
• Wang Jen Hung
• Pan Shing-Chyang

Classifications

• H10P50/283 Primary

  by chemical means · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title