Etch stop layer in integrated circuits

Patent metadata

Field	Value
Publication number	US-10090242-B2
Application number	US-201615244961-A
Country	US
Kind code	B2
Filing date	Aug 23, 2016
Priority date	Oct 17, 2014
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.

First claim

What is claimed is:

1. An integrated circuit structure comprising:
a first dielectric layer; and
an etch stop layer comprising:
a first sub layer comprising a metal nitride over the first dielectric layer; and
a second sub layer overlying and contacting the first sub layer, wherein the second sub layer comprises a metal compound comprising a metal carbo-nitride or a metal oxynitride, with the first sub layer and the second sub layer comprising a same metal, and wherein the first sub layer has a first ratio of an atomic percentage of metal to an atomic percentage of nitrogen, and the second sub layer has a second ratio of an atomic percentage of metal to an atomic percentage of nitrogen, and the second ratio is equal to the first ratio.

2. The integrated circuit structure of claim 1 , wherein the second sub layer comprises carbon.

3. The integrated circuit structure of claim 2 , wherein the second sub layer is substantially free from oxygen.

4. The integrated circuit structure of claim 1 further comprising a third sub layer underlying the first sub layer, wherein the third sub layer comprises a metal carbide.

5. The integrated circuit structure of claim 1 , wherein the first sub layer is substantially free from carbon and oxygen.

6. The integrated circuit structure of claim 1 further comprising:
a conductive line in the first dielectric layer;
a second dielectric layer over the etch stop layer; and
a via comprising a portion in the second dielectric layer, wherein the via further penetrates through the etch stop layer to electrically couple to the conductive line.

7. An integrated circuit structure comprising:
a first dielectric layer;
an etch stop layer over the first dielectric layer, the etch stop layer comprising:
a first sub layer comprising a metal carbide;
a second sub layer over the first sub layer, wherein the second sub layer comprises a metal nitride; and
a third sub layer overlying the second sub layer, wherein the third sub layer comprises a metal compound comprising an element selected from carbon and oxygen, and the metal compound has a same metal as the second sub layer;

a second dielectric layer over the etch stop layer; and
a via comprising a portion in the second dielectric layer, wherein the via penetrates through the etch stop layer.

8. The integrated circuit structure of claim 7 , wherein the third sub layer comprises a metal carbide.

9. The integrated circuit structure of claim 8 , wherein the third sub layer further comprises nitrogen.

10. The integrated circuit structure of claim 7 , wherein the first sub layer has a same metal as the second sub layer and the third sub layer.

11. The integrated circuit structure of claim 7 , wherein the second sub layer has a thickness smaller than about 50 Å.

12. An integrated circuit structure comprising:
a first low-k dielectric layer;
an etch stop layer comprising:
a first sub layer comprising a metal carbide over and in contact with the first low-k dielectric layer;
a second sub layer over and in contact with the first sub layer, wherein the second sub layer comprises a metal nitride; and
a third sub layer over and in contact with the second sub layer, wherein the third sub layer comprises a metal compound comprising nitrogen and an element selected from carbon and oxygen, and wherein the first sub layer, the second sub layer, and the third sub layer comprise a same metal, wherein the third sub layer comprises a metal carbo-nitride or a metal oxynitride, and the second sub layer has a first ratio of an atomic percentage of the same metal to an atomic percentage of nitrogen or oxygen, and the third sub layer has a second ratio of an atomic percentage of the same metal to an atomic percentage of nitrogen or oxygen, and the second ratio is equal to the first ratio;

a second low-k dielectric layer over and in contact with the etch stop layer; and
a via comprising a portion in the second low-k dielectric layer, wherein the via penetrates through the etch stop layer.

13. The integrated circuit structure of claim 12 , wherein the third sub layer comprises the metal carbo-nitride.

14. The integrated circuit structure of claim 12 , wherein the third sub layer comprises the metal oxynitride.

15. The integrated circuit structure of claim 12 , wherein the second sub layer is substantially free from carbon.

16. The integrated circuit structure of claim 12 , wherein the first sub layer is substantially free from nitrogen.

17. The integrated circuit structure of claim 16 , wherein the first sub layer is substantially free from both carbon and nitrogen.

18. The integrated circuit structure of claim 6 , wherein the second dielectric layer is in physical contact with the etch stop layer.

19. The integrated circuit structure of claim 4 , wherein the third sub layer comprises a bottom surface contacting the first dielectric layer.

20. The integrated circuit structure of claim 7 , wherein the first sub layer physically contacts a top surface of the first dielectric layer, and the third sub layer physically contacts a bottom surface of the second dielectric layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Jangjian Shiu-Ko
• Hong Tsung-Hsuan
• Lin Chun Che
• Wu Chih-Nan

Classifications

• H10W20/037

  the barrier, adhesion or liner layers being on top of a main fill metal · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/096

  by contacting with gases, liquids or plasmas · CPC title

• H10W20/084

  for dual-damascene structures · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title