Method for cleaning via of interconnect structure of semiconductor device structure

Patent metadata

Field	Value
Publication number	US-9761488-B2
Application number	US-201514802734-A
Country	US
Kind code	B2
Filing date	Jul 17, 2015
Priority date	Jul 17, 2015
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A method for forming the semiconductor device structure is provided. The method includes forming a metal layer in a first dielectric layer over a substrate and forming an etch stop layer over the metal layer. The etch stop layer is made of metal-containing material. The method also includes forming a second dielectric layer over the etch stop layer and removing a portion of the second dielectric layer to expose the etch stop layer and to form a via by an etching process. The method further includes performing a plasma cleaning process on the via and the second dielectric layer, and the plasma cleaning process is performed by using a plasma including nitrogen gas (N 2 ) and hydrogen gas (H 2 ).

First claim

What is claimed is:

1. A method for forming a semiconductor device structure, comprising:
forming a metal layer in a first dielectric layer over a substrate;
forming an etch stop layer over the metal layer, wherein the etch stop layer is made of aluminum-containing insulating material;
forming a second dielectric layer over the etch stop layer
removing a portion of the second dielectric layer to expose the etch stop layer and to form a via by an etching process; and
performing a plasma cleaning process on the via and the second dielectric layer, wherein the plasma cleaning process is performed by using a plasma comprising nitrogen gas (N 2 ) and hydrogen gas (H 2 ).

2. The method for forming the semiconductor device structure as claimed in claim 1 , wherein a ratio of the flow rate of nitrogen gas (N 2 ) to the flow rate of hydrogen gas (H 2 ) is in a range from about 2/1 to about 4/1.

3. The method for forming the semiconductor device structure as claimed in claim 1 , further comprising:
after the plasma cleaning process, performing a wet cleaning process on the second dielectric layer.

4. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the etching process is performed by using an etch gas comprising fluorine-containing gas.

5. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the etching process and the plasma cleaning process are performed in the same chamber.

6. The method for forming the semiconductor device structure as claimed in claim 1 , further comprising:
forming a barrier layer under the metal layer, wherein the metal layer is surrounded by the barrier layer; and
forming a capping layer over the metal layer.

7. The method for forming the semiconductor device structure as claimed in claim 1 , further comprising:
filling a conductive material into the via to form a conductive structure, wherein the conductive structure is electrically connected to the metal layer.

8. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the aluminum-containing insulating material is aluminum nitride.

9. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the aluminum-containing insulating material is aluminum oxide.

10. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the aluminum-containing insulating material is aluminum oxynitride.

11. A method for forming a semiconductor device structure, comprising:
forming an etch stop layer over a substrate, wherein the etch stop layer is made of aluminum-containing insulating material;
forming a dielectric layer over the etch stop layer;
forming an antireflection layer over the dielectric layer;
forming a hard mask layer over the antireflection layer;
forming a patterned photoresist layer over the hard mask layer;
etching a portion of the antireflection layer by using the patterned photoresist layer as a mask and by performing a first etching process;
etching through the antireflection layer and etching a portion of the dielectric layer by performing a second etching process to form an opening in the dielectric layer; and
etching through the dielectric layer and the etch stop layer by performing a third etching process to form a via portion; and
performing a plasma cleaning process on the via and the dielectric layer, wherein the plasma cleaning process is performed by using a plasma comprising nitrogen gas (N 2 ) and hydrogen gas (H 2 ).

12. The method for forming the semiconductor device structure as claimed in claim 11 , wherein a ratio of the flow rate of nitrogen gas (N 2 ) to the flow rate of hydrogen gas (H 2 ) is in a range from about 2/1 to about 4/1.

13. The method for forming the semiconductor device structure as claimed in claim 11 , further comprising:
after the plasma cleaning process, performing a wet cleaning process over the dielectric layer.

14. The method for forming the semiconductor device structure as claimed in claim 13 , wherein the first etching process, the second etching process, the third etching process and the plasma cleaning process are performed in the same chamber.

15. The method for forming the semiconductor device structure as claimed in claim 11 , further comprising:
forming a buffer layer between the dielectric layer and the antireflection layer, wherein during the second etching process, an etch rate of the buffer layer is between an etch rate of the antireflection layer and an etch rate of the dielectric layer.

16. The method for forming the semiconductor device structure as claimed in claim 11 , further comprising:
forming a metal layer over a substrate; and
forming a capping layer on the metal layer, wherein the etch stop layer is formed directly on the capping layer.

17. The method for forming the semiconductor device structure as claimed in claim 11 , further comprising:
patterning the hard mask layer to form a patterned hard mask layer; and
pattering the dielectric layer by the patterned hard mask layer, such that a trench portion over the via portion is formed while performing the third etching process.

18. The method for forming the semiconductor device structure as claimed in claim 17 , further comprising:
filling a conductive material into the via portion and the trench portion to form a dual damascene structure.

19. The method for forming the semiconductor device structure as claimed in claim 11 , wherein a metal oxide layer is formed on the etch stop layer after performing the third etching process, and the plasma cleaning process is configured to remove the metal oxide layer.

20. A method for forming a semiconductor device structure, comprising:
forming a metal layer over a substrate;
forming an etch stop layer over the metal layer, wherein the etch stop layer is made of aluminum-containing insulating material;
forming a dielectric layer over the etch stop layer;
removing a portion of the dielectric layer to expose the etch stop layer and to form a via, wherein a metal oxide layer is formed on the etch stop layer and the sidewalls of the via; and
performing a plasma cleaning process to remove the metal oxide layer, wherein the plasma cleaning process is performed by using a plasma comprising nitrogen gas (N 2 ) and hydrogen gas (H 2 ).

21. The method for forming the semiconductor device structure as claimed in claim 20 , further comprising:
forming an adhesion layer between the etch stop layer and the dielectric layer.

22. The method for forming the semiconductor device structure as claimed in claim 20 , wherein the plasma cleaning process is operated at a temperature in a range from about 10 degrees to about 100 degrees.

23. The method for forming the semiconductor device structure as claimed in claim 20 , wherein a ratio of the flow rate of nitrogen gas (N 2 ) to the flow rate of hydrogen gas (H 2 ) is in a range from about 2/1 to about 4/1.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Cheng Tai-Shin
• Chang Che-Cheng
• Chen Wei-Ting
• Shiao Wei-Yin

Classifications

• H10P76/2043

  using an anti-reflective coating · CPC title

• H10P70/234

  the processing being the formation of vias or contact holes · CPC title

• H10P70/27

  during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers · CPC title

• H10P50/283 Primary

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title