Semiconductor device and a method for fabricating the same

Patent metadata

Field	Value
Publication number	US-11764218-B2
Application number	US-202117353533-A
Country	US
Kind code	B2
Filing date	Jun 21, 2021
Priority date	Feb 10, 2016
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of p-type field effect transistors (PFETs) having three different threshold voltages, wherein:
the plurality of PFETs include a first PFET having a first gate structure including a first barrier layer disposed over a first gate dielectric layer, and a first work function adjustment material (WFM) layer disposed over the first barrier layer,
the first WFM layer includes a TiN layer and a layer of aluminum containing material disposed over the TiN layer, and
the first PFET has a lowest threshold voltage in an absolute value among the plurality of PFETs.

2. The semiconductor device of claim 1 , wherein the aluminum containing material is TiAlC.

3. The semiconductor device of claim 1 , wherein:
the first gate structure further includes a first adhesion layer disposed directly on the first WFM layer and a first metal layer disposed on the first adhesion layer.

4. The semiconductor device of claim 3 , wherein:
the first adhesion layers includes a TiN layer, and
the first metal layers includes a W layer.

5. The semiconductor device of claim 1 , wherein a thickness of the layer of the aluminum containing material is in a range from 0.5 nm to 10 nm.

6. The semiconductor device of claim 1 , wherein a thickness of the TiN layer in the first WFM layer is 3.5 nm to 8.5 nm.

7. The semiconductor device of claim 1 , wherein the first barrier layer includes a TaN layer.

8. A semiconductor device, comprising:
a first n-channel FET (NEFT) including a first gate structure and having a threshold voltage Vn 1 ;
a second NFET including a second gate structure and having a threshold voltage Vn 2 ; and
a third NFET including a third gate structure and having a threshold voltage Vn 3 , wherein:
Vn 1 <Vn 2 <Vn 3 in absolute values,
the first gate structure includes a first work function adjustment material (WFM) layer, the second gate structure includes a second WFM layer, and the third gate structure includes a third WFM layer,
at least one of thickness or material of the first to third WFM layers is different from each other, and
each of the first, second and third WFM layers includes an aluminum containing layer.

9. The semiconductor device of claim 8 , wherein:
each of the second and third WFM layers includes a TiN layer, and
a thickness of the TiN of the second WFM layer is smaller than a thickness of the third WFM layer.

10. The semiconductor device of claim 8 , wherein the TiN layer is disposed below the Al containing layer.

11. The semiconductor device of claim 8 , wherein the aluminum containing layer includes TiAlC.

12. The semiconductor device of claim 8 , wherein:
the first, second and third WFM layers are formed over a first conductive layer disposed over a gate dielectric layer, and
a second conductive layer is disposed over each of the first, second and third WFM layers with a third conductive layer interposed therebetween.

13. The semiconductor device of claim 12 , wherein:
the first conductive layer is a TaN layer,
the second conductive layer includes a W layer, and
the third conductive layer includes a TiN layer.

14. A semiconductor device, comprising:
a first p-channel FET including a first gate structure and having a threshold voltage Vp 1 ;
a second p-channel FET including a second gate structure and having a threshold voltage Vp 2 ; and
a third p-channel FET including a third gate structure and having a threshold voltage Vp 3 , wherein:
Vp 1< Vp 2< Vp 3,

the first gate structure includes a first work function adjustment material (WFM) layer, the second gate structure includes a second WFM layer, and the third gate structure includes a third WFM layer,
at least one of thickness and material of the first to third WFM layers is different from each other,
at least two of the first, second or third WFM layers include a first layer made of the first material and a second layer made of a second material different from the first material, and
the first layer is formed over the second layer.

15. The semiconductor device of claim 14 , wherein a thickness of the second layer increases in the order of the first WFM layer, the second WFM layer and the third WFM layer.

16. The semiconductor device of claim 14 , wherein the second material is TiN.

17. The semiconductor device of claim 14 , wherein the first material is TiAlC.

18. The semiconductor device of claim 14 , wherein the first, second and third WFM layers are formed over a first conductive layer disposed over a gate dielectric layer.

19. The semiconductor device of claim 18 , wherein a second conductive layer is disposed over each of the first, second and third WFM layers with a third conductive layer interposed therebetween.

20. The semiconductor device of claim 19 , wherein:
the first conductive layer is a TaN layer,
the second conductive layer includes a W layer, and
the third conductive layer includes a TiN layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liao Shun-Jang
• Liao Chia-Chun
• Wang Shu-Hui
• Chang Shih-Hsun

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0177

  the gate conductors having different materials or different implants · CPC title