Perfectly shaped controlled nanowires

Patent metadata

Field	Value
Publication number	US-9406748-B1
Application number	US-201514947444-A
Country	US
Kind code	B1
Filing date	Nov 20, 2015
Priority date	Nov 20, 2015
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A fin stack structure is provided on an insulator layer. The fin stack structure comprises, from bottom to top, a first semiconductor fin portion, a dielectric fin portion, a second semiconductor fin portion and a hard mask fin portion. A sacrificial gate structure is formed on a portion of the fin stack structure. The hard mask fin portion and the dielectric fin portion not located beneath the sacrificial gate structure are removed. An epitaxial semiconductor material structure is then formed from exposed surfaces of each semiconductor fin portion. The sacrificial gate structure is then removed. Next, remaining portions of the hard mask fin portion and the dielectric fin portion are removed. The insulating layer is then recessed. After recessing the insulator layer, the first and second semiconductor fin portions are suspended and are stacked one atop the other.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, said method comprising:
providing at least one fin stack structure on an insulator layer, said at least one fin stack structure comprising, from bottom to top, a first semiconductor fin portion, a dielectric fin portion, a second semiconductor fin portion and a hard mask fin portion;
forming at least one sacrificial gate structure on a portion of said at least one fin stack structure;
removing said hard mask fin portion and said dielectric fin portion that are not located beneath said at least one sacrificial gate structure;
forming an epitaxial semiconductor material structure from exposed surfaces of said first semiconductor fin portion and said second semiconductor fin portion not covered by said at least one sacrificial gate structure;
removing said at least one sacrificial gate structure;
removing remaining portions of said hard mask fin portion and remaining portions of said dielectric fin portion that were previously located beneath said at least one sacrificial gate structure; and
recessing said insulating layer, wherein after said recessing said insulator layer, said first semiconductor fin portion and said second semiconductor fin portion are suspended and are stacked one atop the other.

2. The method of claim 1 , further comprising forming a functional gate structure wrapping around said first semiconductor fin portion and said second semiconductor fin portion.

3. The method of claim 1 , wherein said at least one fin stack structure includes at least one more additional material stack of, from bottom to top, an additional dielectric fin portion and an additional semiconductor fin portion located between said second semiconductor fin portion and said hard mask fin portion.

4. The method of claim 1 , wherein said providing said at least one fin stack structure on said insulator layer comprises:
providing, in any order, a first substrate comprising, from bottom to top, a handle substrate, a first insulator layer, a first semiconductor material layer, and a first dielectric layer, and a second substrate comprising, from bottom to top, a second handle substrate, a second insulator layer, a second semiconductor material layer and a second dielectric layer;
bonding said second dielectric layer of said second substrate to said first dielectric layer of said first substrate;
removing, after said bonding, said second handle substrate and said second insulator layer;
forming a hard mask material layer on an exposed surface of said second semiconductor material layer; and
patterning said hard mask material layer, said second semiconductor material layer, said second dielectric layer, said first dielectric layer and said first semiconductor material layer to provide said at least one fin stack structure, wherein a remaining portion of said first and second dielectric layers provide said dielectric fin portion.

5. The method of claim 4 , wherein said patterning comprises a sidewall image transfer process.

6. The method of claim 1 , wherein said removing said hard mask fin portion and said dielectric fin portion that are not located beneath said at least one sacrificial gate comprises an etching process.

7. The method of claim 1 , wherein said forming said epitaxial semiconductor material structure comprises a selective epitaxial growth process.

8. The method of claim 1 , wherein said removing remaining portions of said hard mask fin portion and remaining portions of said dielectric fin portion that were previously located beneath said at least one sacrificial gate structure comprises an etching process.

9. The method of claim 1 , wherein said first and second semiconductor fin portions comprise a same semiconductor material, and said first and second semiconductor fin portions have a same shape and dimension.

10. The method of claim 1 , wherein said first and second semiconductor fin portions comprise different semiconductor materials, and said first and second semiconductor fin portions have a same shape and dimension.

11. The method of claim 2 , wherein said functional gate structure comprises a gate dielectric portion and a gate conductor portion, wherein said gate dielectric portion is present entirely around said first semiconductor fin portion and said second semiconductor fin portion that are suspended and are stacked one atop the other.

12. The method of claim 11 , wherein after recessing said insulator layer and said forming said functional gate structure, a remaining portion of said insulator layer has a topmost surface contacting a portion of said gate conductor portion of said functional gate structure and a bottommost surface contacting a topmost surface of a handle substrate.

13. The method of claim 1 , wherein during said removing said hard mask fin portion and said dielectric fin portion that are not located beneath said at least one sacrificial gate structure, said at least ones sacrificial gate structure serves as an anchoring structure.

14. The method of claim 13 , wherein during said removing remaining portions of said hard mask fin portion and remaining portions of said dielectric fin portion that were previously located beneath said at least one sacrificial gate structure, said epitaxial semiconductor material structure severs as an anchoring structure.

15. The method of claim 1 , wherein said recessing said insulator layer comprises a selective etching process.

Assignees

• IBM

Inventors

• Balakrishnan Karthik
• Cheng Kangguo
• Doris Bruce B
• Hashemi Pouya
• Reznicek Alexander

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title

• H10P10/128

  by direct semiconductor to semiconductor bonding · CPC title