Scalar core integration

Patent metadata

Field	Value
Publication number	US-11762804-B2
Application number	US-202217868448-A
Country	US
Kind code	B2
Filing date	Jul 19, 2022
Priority date	Mar 15, 2019
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

First claim

The invention claimed is:

1. An apparatus comprising:
a scalar processor complex comprising a plurality of scalar processor cores;
a vector processor complex comprising a plurality of vector processor cores;
a hardware accelerator bank comprising a tensor core to perform matrix processing for deep learning operations using a plurality of operand precisions; and
a pre-processor communicably coupled to the scalar processor complex, the vector processor complex, and the hardware accelerator bank, wherein the pre-processor to:
receive a binary translation of a code segment of a plurality of code segments corresponding to a set of workload instructions for a graphics workload from a host processor;
analyze operations of the binary translation to identify whether the operations are suitable for execution by one of the scalar processor complex, the vector processor complex, or the hardware accelerator bank; and
assigning the operations of the binary translation to the one of the scalar processor complex, the vector processor complex, or the hardware accelerator bank that is identified as suitable for execution of the operations.

2. The apparatus of claim 1 , wherein the pre-processor is further to continue to process other binary translations of other code segments of the plurality of code segments until the graphics workload is finished.

3. The apparatus of claim 2 , wherein the pre-processor is further to store outputs in a local memory.

4. The apparatus of claim 3 , wherein the pre-processor is further to synchronize the local memory with a memory in the host processor after the graphics workload is finished processing.

5. The apparatus of claim 3 , wherein the pre-processor is further to synchronize an execution marker with the host processor after the graphics workload is finished processing.

6. The apparatus of claim 1 , wherein the operations comprises at least one of a stack push operation, a stack pop operation, a register spill operation, a register fill operation, a read operation, or a write operation.

7. A computer-implemented method comprising:
receiving, by a pre-processor of a graphics processing device, a binary translation of a code segment of a plurality of code segments corresponding to a set of workload instructions for a graphics workload from a host processor, wherein the pre-processor is communicably coupled to a scalar processor complex comprising a plurality of scalar processor cores, to a vector processor complex comprising a plurality of vector processor cores, and to a hardware accelerator bank comprising a tensor core to perform matrix processing for deep learning operations using a plurality of operand precisions;
analyzing, by the pre-processor, operations of the binary translation to identify whether the operations are suitable for execution by one of the scalar processor complex, the vector processor complex, or the hardware accelerator bank; and
assigning, by the pre-processor, the operations of the binary translation to the one of the scalar processor complex, the vector processor complex, or the hardware accelerator bank that is identified as suitable for execution of the operations.

8. The computer-implemented method of claim 7 , further comprising continuing to process other binary translations of other code segments of the plurality of code segments until the graphics workload is finished.

9. The computer-implemented method of claim 8 , further comprising storing outputs in a local memory.

10. The computer-implemented method of claim 9 , further comprising synchronizing the local memory with a memory in the host processor after the graphics workload is finished processing.

11. The computer-implemented method of claim 9 , further comprising synchronizing an execution marker with the host processor after the graphics workload is finished processing.

12. The computer-implemented method of claim 7 , wherein the operations comprises at least one of a stack push operation, a stack pop operation, a register spill operation; a register fill operation, a read operation, or a write operation.

13. A non-transitory computer-readable medium comprising one or more instructions that, when executed on at least one processor, configure the at least one processor to perform operations to:
receiving, by a pre-processor of a graphics processing device of the at least one processor, a binary translation of a code segment of a plurality of code segments corresponding to a set of workload instructions for a graphics workload from a host processor, wherein the pre-processor is communicably coupled to a scalar processor complex comprising a plurality of scalar processor cores, to a vector processor complex comprising a plurality of vector processor cores, and to a hardware accelerator bank comprising a tensor core to perform matrix processing for deep learning operations using a plurality of operand precisions;
analyzing, by the pre-processor, operations of the binary translation to identify whether the operations are suitable for execution by one of the scalar processor complex, the vector processor complex, or the hardware accelerator bank; and
assigning, by the pre-processor, the operations of the binary translation to the one of the scalar processor complex, the vector processor complex, or the hardware accelerator bank that is identified as suitable for execution of the operations.

14. The non-transitory computer-readable medium of claim 13 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to continue to process other binary translations of other code segments of the plurality of code segments until the graphics workload is finished.

15. The non-transitory computer-readable medium of claim 14 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to store outputs in a local memory.

16. The non-transitory computer-readable medium of claim 15 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to synchronize the local memory with a memory in the host processor after the graphics workload is finished processing.

17. The non-transitory computer-readable medium of claim 15 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to synchronize an execution marker with the host processor after the graphics workload is finished processing.

18. The non-transitory computer-readable medium of claim 13 , wherein the operations comprise at least one of a stack push operation, a stack pop operation, a register spill operation; a register fill operation, a read operation, or a write operation.

19. A system comprising:
a local memory;
a host processor;
a scalar processor complex comprising a plurality of scalar processor cores;
a vector processor complex comprising a plurality of vector processor cores;
a hardware accelerator bank comprising a tensor core to perform matrix processing for deep learning operations using a plurality of operand precisions; and
a pre-processor communicably coupled to the local memory, the host processor, the scalar processor complex, the vector processor complex, and the hardware accelerator bank, the pre-processor to:
receive a binary translation of a code segment of a plurality of code segments corresponding to a set of workload instructions for a graphics workload from a host processor;

Assignees

• Intel Corp

Inventors

• Ray Joydeep
• Anantaraman Aravindh
• Appu Abhishek R
• Koker Altug
• Ould-Ahmed-Vall Elmoustapha
• Andrei Valentin
• Maiyuran Subramaniam
• Galoppo Von Borries Nicolas
• George Varghese
• Macpherson Mike
• Ashbaugh Ben
• Ramadoss Murali
• Vemulapalli Vikranth
• Sadler William
• Pearce Jonathan
• Kim Sungye

Classifications

• G06F9/5044 Primary

  considering hardware capabilities · CPC title

• G06F15/8069 Primary

  using a cache · CPC title

• G06F9/30163

  with implied specifier, e.g. top of stack · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title