Scalar core integration

Patent metadata

Field	Value
Publication number	US-11409693-B2
Application number	US-202117321885-A
Country	US
Kind code	B2
Filing date	May 17, 2021
Priority date	Mar 15, 2019
Publication date	Aug 9, 2022
Grant date	Aug 9, 2022

Abstract

Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

First claim

The invention claimed is:

1. An apparatus comprising:
a scalar processor complex comprising a plurality of scalar processor cores;
a vector processor complex comprising a plurality of vector processor cores;
a hardware accelerator bank comprising a tensor core to perform matrix processing for deep learning operations using a plurality of operand precisions; and
a pre-processor communicably coupled to the scalar processor complex, the vector processor complex, and the hardware accelerator bank, the pre-processor to:
receive a set of workload instructions for a graphics workload from a host processor;
determine a first subset of operations in the set of operations that is suitable for execution by the scalar processor complex, a second subset of operations in the set of operations that is suitable for execution by the vector processor complex, and a third subset of operations in the set of operations that is suitable for execution by the hardware accelerator bank;
assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs;
assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs; and
assign the third subset of operations to the hardware accelerator bank for execution to generate a third set of outputs.

2. The apparatus of claim 1 , the pre-processor to:
continue to process workload instructions until the workload is finished.

3. The apparatus of claim 2 , the pre-processor to:
store the first set of outputs and the second set of outputs in a local memory.

4. The apparatus of claim 3 , the pre-processor to:
synchronize the local memory with a memory in the host processor after the workload is finished processing.

5. The apparatus of claim 3 , the pre-processor to:
synchronize an execution marker with the host processor after the workload is finished processing.

6. The apparatus of claim 1 , the pre-processor to:
receive a binary translation of a code; and
divide the binary translation into a plurality of code segments.

7. The apparatus of claim 1 , wherein the first subset of operations comprises at least one of a stack push operation, a stack pop operation, a register spill operation; a register fill operation, a read operation, or a write operation.

8. A computer-implemented method comprising:
receiving, by a pre-processor of a graphics processing device, a set of workload instructions for a graphics workload from a host processor, wherein the pre-processor is communicably coupled to a scalar processor complex comprising a plurality of scalar processor cores, to a vector processor complex comprising a plurality of vector processor cores, and to a hardware accelerator bank comprising a tensor core to perform matrix processing for deep learning operations using a plurality of operand precisions;
determining, by the pre-processor based on an analysis of a binary translation of the set of workload instructions, a first subset of operations in the set of operations that is suitable for execution by the scalar processor complex, a second subset of operations in the set of operations that is suitable for execution by the vector processor complex, and a third subset of operations in the set of operations that is suitable for execution by the hardware accelerator bank;
assigning, by the pre-processor, the first subset of operations to the scalar processor complex for execution to generate a first set of outputs;
assigning, by the pre-processor, the second subset of operations to the vector processor complex for execution to generate a second set of outputs; and
assigning, by the pre-processor, the third subset of operations to the hardware accelerator bank for execution to generate a third set of outputs.

9. The method of claim 8 , further comprising:
continuing to process workload instructions until the workload is finished.

10. The method of claim 9 , further comprising storing the first set of outputs and the second set of outputs in a local memory.

11. The method of claim 10 , further comprising:
synchronizing the local memory with a memory in the host processor after the workload is finished processing.

12. The method of claim 10 , further comprising:
synchronizing an execution marker with the host processor after the workload is finished processing.

13. The method of claim 8 , further comprising:
receiving a binary translation of a code; and
dividing the binary translation into a plurality of code segments.

14. The method of claim 8 , wherein the first subset of operations comprises at least one of a stack push operation, a stack pop operation, a register spill operation; a register fill operation, a read operation, or a write operation.

15. One or more non-transitory computer-readable medium comprising one or more instructions that when executed on at least one processor configure the at least one processor to perform one or more operations to:
receive, by a pre-processor of a graphics processing device of the at least one processor, a set of workload instructions for a graphics workload from a host processor, wherein the pre-processor is communicably coupled to a scalar processor complex comprising a plurality of scalar processor cores, to a vector processor complex comprising a plurality of vector processor cores, and to a hardware accelerator bank comprising a tensor core to perform matrix processing for deep learning operations using a plurality of operand precisions;
determine, by the pre-processor based on an analysis of a binary translation of the set of workload instructions, a first subset of operations in the set of operations that is suitable for execution by the scalar processor complex, a second subset of operations in the set of operations that is suitable for execution by the vector processor complex, and a third subset of operations in the set of operations that is suitable for execution by the hardware accelerator bank;
assign, by the pre-processor, the first subset of operations to the scalar processor complex for execution to generate a first set of outputs;
assign, by the pre-processor, the second subset of operations to the vector processor complex for execution to generate a second set of outputs; and
assign, by the pre-processor, the third subset of operations to the hardware accelerator bank for execution to generate a third set of outputs.

16. The computer-readable medium of claim 15 , comprising one or more instructions that when executed on the at least one processor configure the at least one processor to:
continue to process workload instructions until the workload is finished.

17. The computer-readable medium of claim 16 , comprising one or more instructions that when executed on the at least one processor configure the at least one processor to:
store the first set of outputs and the second set of outputs in a local memory.

18. The computer-readable medium of claim 17 , comprising one or more instructions that when executed on the at least one processor configure the at least one processor to:
synchronize the local memory with a memory in the host processor after the workload is finished processing.

19. The computer-readable medium of claim 17 , comprising one or more instructions that when executed on the at least one processor configure the at least one processor to:
synchronize an execution marker with the host processor after the workload is finished processing.

20. The computer-readable medium of claim 15 ,

Assignees

• Intel Corp

Inventors

• Ray Joydeep
• Anantaraman Aravindh
• Appu Abhishek R
• Koker Altug
• Ould-Ahmed-Vall Elmoustapha
• Andrei Valentin
• Maiyuran Subramaniam
• Galoppo Von Borries Nicolas
• George Varghese
• Macpherson Mike
• Ashbaugh Ben
• Ramadoss Murali
• Vemulapalli Vikranth
• Sadler William
• Pearce Jonathan
• Kim Sungye

Classifications

• G06F15/8069 Primary

  using a cache · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06T15/005

  General purpose rendering architectures · CPC title

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title

• G06F9/5044 Primary

  considering hardware capabilities · CPC title