Self adapting iterative read calibration to retrieve data from memory cells

Patent metadata

Field	Value
Publication number	US-11762599-B2
Application number	US-202217848292-A
Country	US
Kind code	B2
Filing date	Jun 23, 2022
Priority date	Mar 2, 2020
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

A memory sub-system configured to iterative calibrate read voltages, where higher read voltages are calibrated based on the calibration results of lower read voltages. For example, a memory device initially determines first read voltages of a group of memory cells. The memory device calculates a second read voltage optimized to read the group of memory cells according to first signal and noise characteristics measured based on at least one of the first read voltages. A third read voltage is estimated based on an offset of the second read voltage from a corresponding voltage among the first read voltages. Second signal and noise characteristics of the group of memory cells are measured based on the third read voltage. The memory device then calculates a fourth read voltage optimized to read the group of memory cells according to the second signal and noise characteristics.

First claim

What is claimed is:

1. A device, comprising:
memory cells;
a calibration circuit configured to apply a voltage on the memory cells to determine a count of cells having a predetermined state when applied the voltage; and
a controller coupled to the calibration circuit and configured to:
determine first voltages for reading the memory cells;
calibrate a first subset of the first voltages using counts determined by the calibration circuit at voltages configured according to the first subset;
determine a correction to a second subset of the first voltages based on the first subset being calibrated based on the counts; and
calibrate the second subset of the first voltages using counts determined by the calibration circuit.

2. The device of claim 1 , wherein the correction is based on one or more offsets between the first subset of the first voltages before and after being calibrated.

3. The device of claim 2 , wherein the first subset of the first voltages includes a second voltage; the second subset of the first voltages includes a third voltage higher than the second voltage; and the third voltage is calibrated based on a first offset of the second voltage before and after being calibrated.

4. The device of claim 3 , wherein the controller is configured to instruct the calibration circuit to determine first counts at a first plurality of voltages centered at the third voltage being corrected by the first offset of the second voltage.

5. The device of claim 4 , wherein the controller is configured to calibrate the third voltage to a fourth voltage based on the first counts.

6. The device of claim 5 , wherein the controller is configured to determine the fourth voltage according to an estimate of a minimum in count difference over the first plurality of voltages.

7. The device of claim 6 , wherein the first voltages include a fifth voltage higher than the third voltage; and the controller is further configured to:
determine a second offset between the third voltage and the fourth voltage;
determine a second plurality of voltages centered at the fifth voltage being corrected by the second offset; and
instruct the calibration circuit to determine second counts at the second plurality of voltages.

8. The device of claim 7 , wherein the controller is configured to calibrate the fifth voltage to a sixth voltage based on an estimate of a minimum in count difference over the second plurality of voltages.

9. A method, comprising:
applying, by a calibration circuit of a device having memory cells, a voltage on the memory cells to determine a count of cells having a predetermined state when applied the voltage;
determining, by the device, first voltages for reading the memory cells;
calibrating, by the device, a first subset of the first voltages using counts determined by the calibration circuit at voltages configured according to the first subset;
determining, by the device, a correction to a second subset of the first voltages based on the first subset being calibrated based on the counts; and
calibrating, by the device, the second subset of the first voltages using counts determined by the calibration circuit.

10. The method of claim 9 , wherein the correction is based on one or more offsets between the first subset of the first voltages before and after being calibrated.

11. The method of claim 10 , wherein the first subset of the first voltages includes a second voltage; the second subset of the first voltages includes a third voltage higher than the second voltage; and the third voltage is calibrated based on a first offset of the second voltage before and after being calibrated.

12. The method of claim 11 , further comprising:
determining, by the calibration circuit, first counts at a first plurality of voltages centered at the third voltage being corrected by the first offset of the second voltage.

13. The method of claim 12 , wherein the calibrating of the second subset of the first voltages includes calibrating the third voltage to a fourth voltage based on the first counts.

14. The method of claim 13 , wherein the fourth voltage is determined according to an estimate of a minimum in count difference over the first plurality of voltages.

15. The method of claim 14 , wherein the first voltages include a fifth voltage higher than the third voltage; and the method further comprises:
determining a second offset between the third voltage and the fourth voltage;
determining a second plurality of voltages centered at the fifth voltage being corrected by the second offset; and
instructing the calibration circuit to determine second counts at the second plurality of voltages.

16. The method of claim 15 , further comprising:
calibrating the fifth voltage to a sixth voltage based on an estimate of a minimum in count difference over the second plurality of voltages.

17. A memory sub-system, comprising:
a processing device; and
a memory device, comprising:
memory cells;
a calibration circuit configured to apply a voltage on the memory cells to determine a count of cells having a predetermined state when applied the voltage; and
a controller coupled to the calibration circuit and configured, in response to a read command from the processing device, to:
determine first voltages for reading the memory cells;
calibrate a second voltage in the first voltages using first counts determined by the calibration circuit at a first plurality of voltages configured according to the second voltage;
determine a correction to a third voltage in the first voltages based on the second voltage being calibrated based on the first counts; and
calibrate the third voltage in the first voltages using second counts determined by the calibration circuit.

18. The memory sub-system of claim 17 , wherein the first plurality of voltages are configured to be centered at the third voltage being corrected by a first offset of the second voltage before and after being calibrated.

19. The memory sub-system of claim 18 , wherein the memory device is configured to calibrate the third voltage to a fourth voltage according to an estimate of a minimum in count difference over the first plurality of voltages.

20. The memory sub-system of claim 19 , wherein the first voltages include a fifth voltage higher than the third voltage; and the memory device is further configured to:
determine a second offset between the third voltage and the fourth voltage;
determine the second plurality of voltages centered at the fifth voltage being corrected by the second offset;
instruct the calibration circuit to determine the second counts at the second plurality of voltages; and
calibrate the fifth voltage to a sixth voltage based on an estimate of a minimum in count difference over the second plurality of voltages.

Assignees

• Micron Technology Inc

Inventors

• Alhussien Abdelhakim S
• Parthasarathy Sivagnanam
• Fitzpatrick James
• Khayat Patrick Robert

Classifications

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C11/5642 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G11C16/30

  Power supply circuits · CPC title

• G11C16/3404

  Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells · CPC title