Forming wrap-around silicide contact on finFET

Patent metadata

Field	Value
Publication number	US-9318581-B1
Application number	US-201514952108-A
Country	US
Kind code	B1
Filing date	Nov 25, 2015
Priority date	Sep 23, 2015
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A technique relates to a transistor. Dummy gates are formed on top of an isolation layer and over fins. Pillars are along sides of fins such that trenches separate the pillars from the sides of the fins. The pillars include a first intermediate layer formed on an isolation layer and a second intermediate layer formed on the first intermediate layer. An epitaxial layer is deposited in the trenches such that the epitaxial layer is laterally confined by the pillars. The top of the epitaxial layer forms a triangular shape that extends higher than the pillars. The pillars are removed such that straight sidewalls of the epitaxial layer are exposed. Dummy gates are replaced with replacement gates. A metal silicide contact that wraps around a source part and a drain part of the epitaxial layer is formed, by forming a conductive layer on top of the structure.

First claim

What is claimed is:

1. A method of forming a transistor, the method comprising:
providing a structure including one or more dummy gates on a top of an isolation layer and over one or more fins, a hard mask on top of the one or more dummy gates, and spacers on sides of the one or more dummy gates and the hard mask, wherein the isolation layer is on top of a substrate;
forming pillars along sides of the one or more fins such that trenches separate the pillars from the sides of the one or more fins, the pillars including a first intermediate layer formed on the isolation layer and a second intermediate layer formed on the first intermediate layer;
depositing an epitaxial layer in the trenches such that the epitaxial layer is laterally confined by the pillars, a top of the epitaxial layer forming a triangular shape that extends higher than the pillars;
removing the pillars such that straight sidewalls of the epitaxial layer are exposed;
replacing the one or more dummy gates and the hard mask with one or more replacement gates;
forming a first filling material on top of the structure, such that contact openings in the first filling material are formed over a source part of the epitaxial layer on the one or more fins, a drain part of the epitaxial layer on the one or more fins, and the one or more replacement gates; and
forming a metal silicide contact that wraps around the source part of the epitaxial layer and the drain part of the epitaxial layer, by forming a conductive layer on top of the structure.

2. The method of claim 1 , wherein the conductive layer is formed so as not to connect together the source part, the drain part, and the one or more replacement gates.

3. The method of claim 1 , wherein the conductive layer wraps around the source part of the epitaxial layer and the drain part of the epitaxial layer.

4. The method of claim 3 , further comprising depositing a second filling material on top of the conductive layer; and
planarizing the first filling material, the second filling material, and the conductive layer such that the conductive layer is not continuous, thereby separating the conductive layer from connecting the source part, the drain part, and the one or more replacement gates.

5. The method of claim 1 , wherein the conductive layer comprises a first layer and a second layer, the first layer being deposited on top of the source part of the epitaxial layer, the drain part of the epitaxial layer, the one or more replacement gates, and the isolation layer.

6. The method of claim 5 , wherein the first layer comprises titanium.

7. The method of claim 6 , wherein the second layer comprises titanium nitride.

8. The method of claim 1 , wherein the metal silicide contact that wraps arounds the source part of the epitaxial layer and the drain part of the epitaxial layer is assisted in formation by annealing.

9. The method of claim 1 , wherein the straight sidewalls and the triangular shape of the top of the epitaxial layer form a pencil shape; and
wherein the metal silicide contact wraps around the pencil shape of the epitaxial layer.

10. The method of claim 9 , wherein the one or more fins have a fin pitch of less than 42 nanometers.

11. A method of forming a transistor, the method comprising:
providing a structure including one or more dummy gates on a top of an isolation layer and over one or more fins, a hard mask on top of the one or more dummy gates, and spacers on sides of the one or more dummy gates and the hard mask, wherein the isolation layer is on top of a substrate;
depositing a first intermediate layer on top of the structure, wherein first trenches having been covered in the first intermediate layer are on sides of the one or more fins;
depositing a second intermediate layer on top of the structure, such that the first trenches are filled, wherein a portion of the second intermediate layer is recessed to correspond to a height to fill the first trenches;
removing a portion of the first intermediate layer that is not covered by the second intermediate layer, such that second trenches are formed on the sides of the one or more fins, wherein pillars are formed of the second intermediate layer on top of the first intermediate layer not having been removed;
depositing an epitaxial layer in the second trenches such that the epitaxial layer is laterally confined by the pillars, a top of the epitaxial layer forming a triangular shape that extends higher than the pillars;
removing the pillars of the second intermediate layer on top of the first intermediate layer, such that straight sidewalls of the epitaxial layer are exposed;
replacing the one or more dummy gates and the hard mask with one or more replacement gates;
forming a first filling material on top of the structure, such that contact openings in the first filling material are formed over a source part of the epitaxial layer on the one or more fins, a drain part of the epitaxial layer on the one or more fins, and the one or more replacement gates;
forming a metal silicide contact that wraps around the source part of the epitaxial layer of the one or more fins and the drain part of the epitaxial layer of the one or more fins, by depositing a conductive layer on top of the structure, wherein the conductive layer wraps around the source part of the epitaxial layer and the drain part of the epitaxial layer;
depositing a second filling material on top of the first filling material; and
planarizing the first filling material, the second filling material, and the conductive layer such that the conductive layer is not continuous, thereby separating the conductive layer from connecting the source part, the drain part, and the one or more replacement gates.

Assignees

• IBM

Inventors

• Guo Dechao
• Jagannathan Hemanth
• Liu Zuoguang
• Mochizuki Shogo

Classifications

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0133

  Manufacturing common source or drain regions between multiple IGFETs · CPC title

• H10D86/011

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title