Memory device supporting DBI interface and operating method of memory device

Patent metadata

Field	Value
Publication number	US-11756592-B2
Application number	US-202117477931-A
Country	US
Kind code	B2
Filing date	Sep 17, 2021
Priority date	Sep 29, 2020
Publication date	Sep 12, 2023
Grant date	Sep 12, 2023

Abstract

A memory device includes a memory cell array, a page buffer, a control logic circuit, a plurality of input/output pins, a data bus inversion (DBI) pin, and an interface circuit. The page buffer is connected to the memory cell array. The control logic circuit is configured to control an operation of the memory cell array. The plurality of input/output pins receive a plurality of data signals from the controller. The DBI pin receives a DBI signal from the controller. The interface circuit count a first number of bits having a logic value of 1 and a second number of bits having a logic value of 0 from the data signals and the DBI signal and provide the data signals to the page buffer or the control logic circuit based on the first number and the second number.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell array including a plurality of memory cells;
a page buffer connected to the memory cell array;
a control logic circuit configured to control an operation of the memory cell array;
a plurality of input/output pins configured to respectively receive a plurality of data signals from a controller;
a data bus inversion (DBI) pin configured to receive a DBI signal from the controller; and
an interface circuit configured to count a first number of bits having a logic value of 1 and a second number of bits having a logic value of 0 from the plurality of data signals and the DBI signal and provide the plurality of data signals to the page buffer or the control logic circuit based on the first number of bits and the second number of bits.

2. The memory device of claim 1 , wherein the interface circuit is further configured to:
provide the plurality of data signals to the page buffer when the first number of bits is less than or equal to the second number of bits, and
provide the plurality of data signals to the control logic circuit when the first number of bits is greater than the second number of bits.

3. The memory device of claim 1 , wherein the interface circuit comprises a data signal decoder configured to receive the plurality of data signals from the plurality of input/output pins and receive the DBI signal from the DBI pin,
the data signal decoder is further configured to determine that the plurality of data signals includes data when the first number of bits is less than or equal to the second number of bits, and
the data signal decoder is further configured to determine that the plurality of data signals includes a command or an address when the first number of bits is greater than the second number of bits.

4. The memory device of claim 3 , wherein the interface circuit further comprises a DBI decoder configured to generate decoded data by DBI decoding the data based on the DBI signal and provide the decoded data to the page buffer.

5. The memory device of claim 4 , wherein the control logic circuit is further configured to control a write operation of the decoded data from the page buffer to the memory cell array based on the command and the address.

6. The memory device of claim 4 , wherein the interface circuit further comprises:
a plurality of data signal receivers respectively connected to the plurality of input/output pins; and
a DBI signal receiver connected to the DBI pin, and
the data signal decoder is further configured to receive the plurality of data signals from the plurality of data signal receivers and receive the DBI signal from the DBI signal receiver.

7. The memory device of claim 4 , wherein the interface circuit further comprises:
a plurality of data signal receivers respectively connected to the plurality of input/output pins; and
a DBI signal receiver connected to the DBI pin, the data signal decoder is further configured to receive the plurality of data signals from the plurality of data signal receivers, and
the DBI decoder is further configured to receive the DBI signal from the DBI signal receiver.

8. The memory device of claim 3 , wherein, when the plurality of data signals includes the data, the DBI signal is at an enable level or a disable level according to the data, and,
when the plurality of data signals includes the command or the address, the DBI signal is at the disable level.

9. The memory device of claim 3 , wherein, when the plurality of data signals includes the data, the DBI signal is at a disable level, and,
when the plurality of data signals includes the command or the address, the DBI signal is at an enable level.

10. The memory device of claim 3 , wherein the control logic circuit comprises:
a command decoder configured to receive the command from the interface circuit and decode the command; and
an address decoder configured to receive the address from the interface circuit and decode the address.

11. A memory device comprising:
a plurality of memory chips configured to receive a packet including a header and a data region from a controller,
wherein each of the memory chips comprises:
a plurality of input/output pads configured to respectively receive a plurality of data signals from the controller;
a data bus inversion (DBI) pad configured to receive a DBI signal from the controller; and
an interface circuit configured to count a first number of bits having a logic value of 1 and a second number of bits having a logic value of 0 from the plurality of data signals and the DBI signal and determine the plurality of data signals as the header or the data region based on the first number of bits and the second number of bits.

12. The memory device of claim 11 , wherein the interface circuit is further configured to:
determine that the plurality of data signals correspond to the data region when the first number of bits is less than or equal to the second number of bits, and
determine that the plurality of data signals correspond to the header when the first number of bits is greater than the second number of bits.

13. The memory device of claim 11 , wherein the packet further comprises a trailer, and
the interface circuit is further configured to determine that the plurality of data signals correspond to the data region when the first number of bits is less than or equal to the second number of bits, and
the interface circuit is further configured to determine that the plurality of data signals correspond to the header or the trailer when the first number of bits is greater than the second number of bits.

14. The memory device of claim 11 , wherein the data region includes a command, an address, or data.

15. The memory device of claim 14 , wherein each of the memory chips further comprises:
a memory cell array including a plurality of memory cells;
a page buffer connected to the memory cell array; and
a control logic circuit configured to control an operation of the memory cell array,
the interface circuit is further configured to determine the data region as the command, the address, or the data based on bits included in a first region of the header, and
the interface circuit is further configured to provide the data to the page buffer and provide the command or the address to the control logic circuit.

16. The memory device of claim 15 , wherein the interface circuit is further configured to determine a selected memory chip from among the plurality of memory chips based on bits included in a second region of the header.

17. The memory device of claim 16 , wherein the interface circuit comprises:
a header decoder configured to determine information included in the data region by decoding bits included in the first region of the header; and
a chip selection decoder configured to determine the selected memory chip by decoding bits included in the second region of the header.

18. The memory device of claim 15 , wherein the interface circuit comprises:
a data signal decoder configured to determine that the plurality of data signals correspond to the data region when the first number of bits is less than or equal to the second number of bits and determine that the plurality of data signals correspond to the header when the first number of bits is greater than the second number of bits; and
a DBI decoder configured to generate a plurality of decoded data signals by DBI decoding the plurality of data signals corresponding to the data region based on the DBI signal.

19. The memo

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jo Youngmin
• Jeong Byunghoon
• Kim Tongsung
• Yoon Chiweon
• Lee Seonkyoo

Classifications

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C7/1048 Primary

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/109

  Control signal input circuits · CPC title

• G11C8/06

  Address interface arrangements, e.g. address buffers · CPC title