Data bus inversion (DBI) encoding based on the speed of operation

Patent metadata

Field	Value
Publication number	US-9798693-B2
Application number	US-201615362385-A
Country	US
Kind code	B2
Filing date	Nov 28, 2016
Priority date	Mar 15, 2013
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

A method for data transmission is described. A signaling speed of operation of an electronic device is determined. A data bus inversion algorithm is selected based on the signaling speed of operation. The selected data bus inversion algorithm is used to encode data. The encoded data and a data bus inversion flag are sent to a receiver over a transmission medium.

First claim

What is claimed is:

1. An apparatus for data transmission, comprising:
a mode controller configured to determine whether a signaling speed of operation of an electronic device is a high-speed mode or a low-speed mode and to select a data bus inversion algorithm based on whether the signaling speed of operation is the high-speed mode or the low-speed mode; and
a transmitter configured to use the selected data bus inversion algorithm to encode data and to send the encoded data and a data bus inversion flag to a receiver over a transmission line.

2. The apparatus of claim 1 , wherein the selected data bus inversion algorithm is one of a DBI-AC algorithm and a DBI-DC algorithm.

3. The apparatus of claim 2 , wherein the selected data bus inversion algorithm is DBI-AC when the signaling speed of operation is the low-speed mode.

4. The apparatus of claim 2 , wherein the selected data bus inversion algorithm is DBI-DC when the signaling speed of operation is the high-speed mode.

5. The apparatus of claim 1 , wherein the signaling speed of operation is communicated to an encoder by a dedicated signal.

6. The apparatus of claim 5 , wherein the dedicated signal is provided through a command address bus.

7. The apparatus of claim 5 , wherein the dedicated signal is provided using an existing data line.

8. The apparatus of claim 1 , wherein the signaling speed of operation is autonomously determined by an encoder.

9. The apparatus of claim 1 , wherein the selected data bus inversion algorithm is used to encode data using a topology that does not comprise feedback.

10. The apparatus of claim 1 , wherein the selected data bus inversion algorithm is used to encode data using a topology that comprises feedback.

11. The apparatus of claim 1 , wherein data bus inversion algorithm encoding is disabled autonomously based on a dynamic disable signal.

12. The apparatus of claim 1 , wherein the transmitter is further configured to generate a termination control signal based on the selected data bus inversion algorithm, and to send the termination control signal to the receiver.

13. The apparatus of claim 1 , further comprising a data bus inversion encoder comprising:
an algorithm selection multiplexer;
an XOR gate that receives parallel unencoded data of an upcoming burst and parallel data of a previous burst;
an inverter;
a majority detection circuit; and
a true/complement multiplexer.

14. The apparatus of claim 13 , wherein the data bus inversion encoder further comprises a frequency detection circuit, and wherein the selected data bus inversion algorithm is based on a relationship between a physical layer clock frequency and a reference frequency.

15. An apparatus for data communication, comprising:
a transmitter comprising a channel configuration module and a data bus inversion encoder, wherein:
the channel configuration module is configured to determine whether a signaling speed of operation of an electronic device is a high-speed mode or a low-speed mode and to select a data bus inversion algorithm based on whether the signaling speed of operation is the high-speed mode or the low-speed mode,
the data bus inversion encoder is configured to use the selected data bus inversion algorithm to encode data, and
the transmitter is configured to send the encoded data and a data bus inversion flag to a receiver over a transmission line.

16. The apparatus of claim 15 , wherein the selected data bus inversion algorithm is one of a DBI-AC algorithm and a DBI-DC algorithm.

17. The apparatus of claim 16 , wherein the selected data bus inversion algorithm is DBI-AC when the signaling speed of operation is the low-speed mode.

18. The apparatus of claim 16 , wherein the selected data bus inversion algorithm is DBI-DC when the signaling speed of operation is the high-speed mode.

19. The apparatus of claim 15 , wherein the selected data bus inversion algorithm is used to encode data using a topology that does not comprise feedback.

20. The apparatus of claim 15 , wherein the selected data bus inversion algorithm is used to encode data using a topology that comprises feedback.

Assignees

• Qualcomm Inc

Inventors

• Hollis Timothy Mowry

Classifications

• G06F13/4286 Primary

  using a handshaking protocol, e.g. RS232C link · CPC title

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F13/4226

  with asynchronous protocol · CPC title

• G06F13/287

  Multiplexed DMA (G06F13/30 takes precedence) · CPC title