Memory systems and devices that support clock-to-clock alignment, training and methods of operating same

Patent metadata

Field	Value
Publication number	US-10593382-B2
Application number	US-201816045887-A
Country	US
Kind code	B2
Filing date	Jul 26, 2018
Priority date	Dec 5, 2017
Publication date	Mar 17, 2020
Grant date	Mar 17, 2020

Abstract

A memory device performs first training including a plurality of loop operations to align a main clock signal and a data clock signal, which are received from a memory controller. A method of operating the memory device includes generating division ratio information indicating a division ratio set based on a frequency ratio of the main clock signal to the data clock signal and transmitting the division ratio information to the memory controller to perform the first training. A first loop operation includes: receiving first phase control information, which is generated based on the division ratio information, from the memory controller, dividing the data clock signal based on the division ratio to generate a division data clock signal, selecting a first phase from among a plurality of phases based on the first phase control information, generating a first comparison target clock signal that is shifted from the division data clock signal by the first phase, comparing a phase of the first comparison target clock signal with a phase of the main clock signal, and transmitting a first phase comparison result to the memory controller.

First claim

What is claimed is:

1. A method of operating a memory device configured to perform first training comprising a plurality of loop operations to align a main clock signal and a data clock signal, which are received from a memory controller, the method comprising generating division ratio information indicating a division ratio set based on a frequency ratio of the main clock signal to the data clock signal and transmitting the division ratio information to the memory controller to perform the first training,
wherein a first loop operation of the loop operations comprises:
receiving first phase control information from the memory controller, the first phase control information being generated based on the division ratio information;
dividing the data clock signal based on the division ratio to generate a division data clock signal, selecting a first phase from among a plurality of phases based on the first phase control information, and generating a first comparison target clock signal, the first comparison target clock signal being shifted from the division data clock signal by the first phase; and
comparing a phase of the first comparison target clock signal with a phase of the main clock signal and transmitting a first phase comparison result to the memory controller.

2. The method of claim 1 , wherein a bit number of the division ratio information is set according to a division ratio range that is supportable by the memory device.

3. The method of claim 2 , wherein, as the division ratio range widens, the bit number of the division ratio information is set to a greater bit number.

4. The method of claim 1 , wherein the transmitting of the division ratio information to the memory controller comprises transmitting the division ratio information to the memory controller through at least one data pad allocated to transmit the division ratio information, from among a plurality of data pads of the memory device.

5. The method of claim 4 , wherein the number of data pads allocated to transmit the division ratio information varies according to the bit number of the division ratio information.

6. The method of claim 1 , wherein the transmitting of the division ratio information to the memory controller comprises transmitting the division ratio information to the memory controller through an interface used to test the memory device.

7. The method of claim 1 , wherein the transmitting of the division ratio information to the memory controller comprises:
receiving mode register set (MRS) bit data for requesting the transmission of the division ratio information, from the memory controller; and
transmitting information including the division ratio information.

8. The method of claim 1 , wherein a unit interval between the plurality of phases is set according to the division ratio.

9. The method of claim 1 , wherein the bit number of the first phase control information is set according to the division ratio or the division ratio range that is supportable by the memory device.

10. The method of claim 1 , wherein the receiving of the first phase control information comprises:
receiving mode register set (MRS) bit data including the first phase control information from the memory controller; and
obtaining the first phase control information from the MRS bit data with reference to an MRS of the memory device.

11. The method of claim 1 , wherein a second loop operation of the loop operations comprises:
receiving second phase control information from the memory controller, the second phase control information being generated based on the first phase comparison result;
selecting a second phase of the phases based on the second phase control information and generating a second comparison target clock signal, the second comparison target clock signal being shifted from the division data clock signal by the second phase; and
comparing a phase of the second comparison target clock signal with the phase of the main clock signal and transmitting the second phase comparison result to the memory controller.

12. The method of claim 1 , wherein the generating of the division ratio information and the transmitting of the division ratio information to the memory controller comprise selecting any one candidate division ratio based on operation frequency information of the memory device, from among a plurality of candidate division ratios according to the frequency ratio of the main clock signal to the data clock signal, and setting the selected candidate division ratio as the division ratio.

13. The method of claim 12 , wherein the operation frequency information is set based on mode register set (MRS) bit data received from the memory controller and includes information related to an operation frequency of the memory device.

14. A method of operating a memory device, the method comprising:
receiving a main clock signal and a data clock signal for a memory operation from a memory controller;
selecting any one of a plurality of candidate division ratios according to a frequency ratio of the main clock signal to the data clock signal as a division ratio and generating division ratio information indicating the division ratio and transmitting the division ratio information to the memory controller; and
receiving phase control information from the memory controller and performing first training by using a comparison target clock signal that is generated from the data clock signal based on the division ratio and the phase control information, the phase control information being generated based on the division ratio information.

15. The method of claim 14 , wherein the comparison target clock signal is a signal that is shifted from a division data clock signal by a phase that is selected from among a plurality of phases based on the phase control information, the division data clock signal being generated by dividing the data clock signal based on the division ratio.

16. The method of claim 15 , wherein the respective phases are separated from one another by a unit interval, and
the comparison target clock signal is generated by selecting a phase corresponding to a bit value of the phase control information from among the phases.

17. The method of claim 14 , wherein the selecting of any one of the candidate division ratios as the division ratio comprises selecting any one of the candidate division ratios as the division ratio based on an operation frequency area of the memory device.

18. A memory device configured to perform a memory operation by using a main clock signal and a data clock signal that are received from a memory controller, the memory device comprising a phase adjustment circuit configured to generate a comparison target clock signal based on a frequency ratio of the main clock signal to the data clock signal to perform first training,
wherein the phase adjustment circuit generates division ratio information indicating a division ratio set based on the frequency ratio, transmitting the division ratio information to the memory controller, receiving phase control information from the memory controller, and generating the comparison target clock signal from the data clock signal based on the division ratio and the phase control information, the phase control information being generated based on the division ratio information.

19. The memory device of claim 18 , further comprising a plurality of data pads configured to transmit and receive data to and from the memory controller,
wherein the memory device transmits the division ratio information to the mem

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Dong-Seok
• Kim Byung-Chul

Classifications

• G11C2207/2254

  Calibration · CPC title

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C7/1093 Primary

  Input synchronization · CPC title

• H03L7/0814

  the phase shifting device being digitally controlled · CPC title

• G06F3/0673

  Single storage device · CPC title