Semiconductor memory apparatus and system using the same

Patent metadata

Field	Value
Publication number	US-9659609-B2
Application number	US-201414329622-A
Country	US
Kind code	B2
Filing date	Jul 11, 2014
Priority date	Apr 3, 2014
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

A semiconductor memory apparatus includes a command input unit configured to generate an internal command in response to an external command and a selective input unit configured to transmit selection signals to one of a first internal circuit. The selective input unit transmits the selection signals to the first internal circuit when the internal command is not a predetermined command and transmits the selection signals to the second internal circuit when the internal command is the predetermined command.

First claim

What is claimed is:

1. A semiconductor memory apparatus comprising:
a command input unit configured to generate an internal command in response to an external command; and
a selective input unit configured to transmit selection addresses to a first internal circuit and data masking/data bus inversion (DM/DBI) information signals to a second internal circuit, wherein the selective input unit transmits the selection addresses to the first internal circuit when the internal command is not activated and transmits the DM/DBI information signals to the second internal circuit when the internal command is activated.

2. The semiconductor memory apparatus according to claim 1 , wherein the activated internal command comprises a read command and a write command.

3. The semiconductor memory apparatus according to claim 2 ,
wherein the selective input unit transmits selection signals to the second internal circuit when the internal command is one of the read command and the write command, and
wherein the selective input unit transmits the selection signals to the first internal circuit when the internal command is an active command.

4. The semiconductor memory apparatus according to claim 3 ,
wherein the first internal circuit comprises an address input unit which is inputted with the selection signals as address signals, and
wherein the second internal circuit comprises a data processing unit which is inputted with the selection signals as the DM/DBI information signals.

5. The semiconductor memory apparatus according to claim 4 , wherein the data processing unit comprises:
a DM/DBI input control section configured to generate first data control signals and second data control signals in response to a DM enable signal, a DBI enable signal and the DM/DBI information signals; and
a data input section configured to determine whether to invert the data inputted thereto by using the second data control signals, and determine whether to mask off the data being outputted by using the first data control signals.

6. The semiconductor memory apparatus according to claim 5 ,
wherein the DM/DBI input control section outputs the DM/DBI information signals as the first data control signals when the DM enable signal is enabled, and outputs the DM/DBI information signals as the second data control signals when the DBI enable signal is enabled, and
wherein the data input section masks off the data being outputted when the first data control signals are inputted, and inverts the data inputted thereto when the second data control signals are inputted.

7. A semiconductor memory apparatus comprising:
an address input unit configured to receive first partial addresses in the form of selection address and second partial addresses in the form of address;
a data processing unit configured to receive data and DM/DBI information signals; and
a selective input unit configured to transmit selection signals, which are inputted from an exterior, as the selection addresses when an internal command is not activated and as the DM/DBI information signals when the internal command is activated, wherein the selection addresses are transmitted to the address input unit and the DM/DBI information signals are transmitted to the data processing unit.

8. The semiconductor memory apparatus according to claim 7 ,
wherein the address input unit receives the entire addresses when an active command is inputted to the semiconductor memory apparatus, and
wherein the address input unit receives only the second partial addresses from the controller when one of a read command and a write command is inputted to the semiconductor memory apparatus.

9. The semiconductor memory apparatus according to claim 7 , wherein the data processing unit inverts data corresponding to the DM/DBI information signals when DM enable signal is enabled and mask off data being transmitted when DBI enable signal is enabled.

10. The semiconductor memory apparatus according to claim 7 ,
wherein the selective input unit outputs the selection signals as the DM/DBI information signals when one of the read command and the write command is inputted, and
wherein the selective input unit outputs the selection signals as the selection addresses when an inputted command is not the read nor write command.

11. A system comprising:
a controller configured to output addresses, selection signals, data and commands; and
a semiconductor memory apparatus configured to be inputted with the addresses, the selection signals, the data and the commands, and use the selection signals as first partial addresses when the commands are not activated and use the selection signals as DM/DBI information signals when the commands are activated.

12. The system according to claim 11 , wherein the controller outputs the first partial addresses as the selection signals when a predetermined command is not activated and outputs the DM/DBI information signals as the selection signals when a predetermined command is factivated.

13. The system according to claim 12 , wherein the controller outputs the DM/DBI information signals as the selection signals when a predetermined command is activated, and outputs the first partial addresses as the selection signals when the predetermined command is not activated.

14. The system according to claim 13 , wherein the controller comprises:
an address control unit configured to output the addresses;
a DM/DBI control unit configured to output the DM/DBI information signals;
a selective output unit configured to be inputted with the first partial addresses and the DM/DBI information signals, and output one of the first partial addresses and the DM/DBI information signals, as the selection signals depending on whether the predetermined command is activated;
a data output unit configured to output the data; and
a command control unit configured to output commands for operating the semiconductor memory apparatus.

15. The system according to claim 14 , wherein the selective output unit outputs the DM/DBI information signals as the selection signals when a command outputted from the command control unit is one of a read command and a write command, and outputs the first partial addresses as the selection signals when the command is a command other than the read command and the write command.

16. The system according to claim 11 , wherein the semiconductor memory apparatus comprises:
an address input unit configured to receive second partial addresses, which are outputted from the address control unit of the controller, and selection addresses;
a selective input unit configured to output the selection signals as one of the selection addresses and DM/DBI information signals depending on whether the predetermined command, which is outputted from the command control unit of the controller, is activated;
a data processing unit configured to invert the data inputted thereto or mask off the data being outputted by using the first data control signals in response to the data outputted from the data output unit of the controller and the DM/DBI information signals; and
a command input unit configured to generate an internal command for controlling an operation of the semiconductor memory apparatus in response to the command outputted from the command control unit of the controller.

17. The system according to claim 16 , wherein the selective input unit transmits the selection signals as the DM/DBI information signals to the data processing unit when the read command or the write command is activated, and transmits the selection signals as the selec

Assignees

• Sk Hynix Inc

Inventors

• Hong Yun Gi

Classifications

• G11C7/1096

  Write circuits, e.g. I/O line write drivers · CPC title

• G11C7/1093

  Input synchronization · CPC title

• G11C7/109

  Control signal input circuits · CPC title

• G11C7/1009 Primary

  Data masking during input/output · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title