Interposers and semiconductor packages including the same

Patent metadata

Field	Value
Publication number	US-11742294-B2
Application number	US-202117306290-A
Country	US
Kind code	B2
Filing date	May 3, 2021
Priority date	Sep 22, 2020
Publication date	Aug 29, 2023
Grant date	Aug 29, 2023

Abstract

A semiconductor package includes a first package substrate; a first semiconductor chip on the first package substrate; a first conductive connector on the first package substrate; and an interposer including a central portion on the first semiconductor chip and an outer portion having the first conductive connector attached thereto. The central portion of the interposer includes a bottom surface defining a recess from a bottom surface of the outer portion of the interposer in a vertical direction that is perpendicular to a top surface of the first package substrate. A thickness in the vertical direction of the outer portion of the interposer is greater than a thickness in the vertical direction of the central portion of the interposer.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a first package substrate;
a first semiconductor chip on the first package substrate;
a first conductive connector on the first package substrate; and
an interposer, the interposer including
a central portion on the first semiconductor chip, and
an outer portion contacting the first conductive connector,

wherein the central portion of the interposer includes a bottom surface facing the first semiconductor chip, the bottom surface defining a recess from a bottom surface of the outer portion of the interposer in a vertical direction that is perpendicular to a top surface of the first package substrate,
a thickness in the vertical direction of the outer portion of the interposer is greater than a thickness in the vertical direction of the central portion of the interposer, and
wherein the central portion protrudes upwardly from the outer portion, so that a top surface of the outer portion is at a lower level than a top surface of the central portion in the vertical direction.

2. The semiconductor package of claim 1 , wherein the top surface of the central portion of the interposer and the top surface of the outer portion of the interposer collectively define a groove in a top surface of the interposer at a border between the top surface of the central portion of the interposer and the top surface of the outer portion of the interposer.

3. The semiconductor package of claim 1 , wherein the central portion of the interposer includes:
a first portion overlapping a top surface of the first semiconductor chip in the vertical direction; and
a second portion extending with a slope between the first portion and the outer portion of the interposer.

4. The semiconductor package of claim 1 , wherein the interposer includes:
a base insulating layer;
an upper protective insulating layer on a top surface of the base insulating layer; and
a lower protective insulating layer on a bottom surface of the base insulating layer, and
a thickness in the vertical direction of the upper protective insulating layer in the outer portion of the interposer is greater than a thickness in the vertical direction of the upper protective insulating layer in the central portion of the interposer.

5. The semiconductor package of claim 4 , wherein the thickness in the vertical direction of the upper protective insulating layer in the outer portion of the interposer is greater than a thickness in the vertical direction of the lower protective insulating layer in the outer portion of the interposer.

6. The semiconductor package of claim 4 , wherein the thickness in the vertical direction of the upper protective insulating layer in the outer portion of the interposer is between about 15 μm and about 40 μm.

7. The semiconductor package of claim 4 , wherein the interposer further includes a spacer protruding from the lower protective insulating layer in the central portion of the interposer toward the first semiconductor chip.

8. The semiconductor package of claim 1 , wherein a portion of the first semiconductor chip is at least partially located in the recess of the central portion of the interposer.

9. The semiconductor package of claim 8 , wherein a height of the recess in the vertical direction is between about 10 μm and about 100 μm.

10. The semiconductor package of claim 1 , further comprising:
a second conductive connector on the outer portion of the interposer;
a second package substrate on the interposer through the second conductive connector; and
a second semiconductor chip on the second package substrate.

11. The semiconductor package of claim 10 , wherein
the second package substrate includes a central portion and an outer portion contacting the second conductive connector, and
a bottom surface of the central portion of the second package substrate defines a recess from a bottom surface of the outer portion of the second package substrate in the vertical direction, the bottom surface of the central portion of the second package substrate facing the interposer.

12. The semiconductor package of claim 10 , wherein the interposer further includes
an upper conductive pad connected to the second conductive connector; and
a dam structure extending along an edge of the upper conductive pad.

13. A semiconductor package, comprising:
a first package substrate;
a first semiconductor chip on the first package substrate;
a first conductive connector on the first package substrate and isolated from direct contact with the first semiconductor chip;
an interposer, the interposer including
a central portion on the first semiconductor chip, and
an outer portion contacting the first conductive connector;

an insulating filler between the first package substrate and the interposer, the insulating filler being in contact with both the first semiconductor chip and the first conductive connector;
a second conductive connector on the outer portion of the interposer;
a second package substrate on the interposer through the second conductive connector; and
a second semiconductor chip on the second package substrate,
wherein a distance in a vertical direction between a bottom surface of the outer portion of the interposer and a top surface of the first package substrate is less than a distance in the vertical direction between a top surface of the first semiconductor chip and the top surface of the first package substrate, the vertical direction being perpendicular to the top surface of the first package substrate,
a top surface of the central portion of the interposer and a top surface of the outer portion of the interposer collectively define a groove in a top surface of the interposer at a border between the top surface of the central portion of the interposer and the top surface of the outer portion of the interposer, and
wherein the central portion protrudes upwardly from the outer portion, so that a top surface of the outer portion is at a lower level than a top surface of the central portion in the vertical direction.

14. The semiconductor package of claim 13 , wherein the interposer includes:
a base insulating layer;
a lower conductive pad on a bottom surface of the base insulating layer and connected to the first conductive connector;
a lower protective insulating layer on the bottom surface of the base insulating layer and including one or more inner surfaces that at least partially define a lower opening that is at least partially filled with the first conductive connector;
an upper conductive pad on a top surface of the base insulating layer and connected to the second conductive connector; and
an upper protective insulating layer on the top surface of the base insulating layer and including one or more inner surfaces that at least partially define an upper opening that is at least partially filled with the second conductive connector.

15. The semiconductor package of claim 14 , wherein a thickness in the vertical direction of the upper protective insulating layer in the outer portion of the interposer is greater than a thickness in the vertical direction of the upper protective insulating layer in the central portion of the interposer.

16. The semiconductor package of claim 14 , wherein the interposer further includes a plurality of spacers protruding from the lower protective insulating layer toward the top surface of the first semiconductor chip.

17. The semiconductor package of claim 14 , wherein the upper protective insulating layer includes a dam structure extending along an edge of the upper conducti

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jongho
• Kim Seunghwan
• Oh Junyoung
• Kim Yonghyun
• Lee Yongkwan
• Lee Junga

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title