Semiconductor package

Patent metadata

Field	Value
Publication number	US-9431374-B2
Application number	US-201514595370-A
Country	US
Kind code	B2
Filing date	Jan 13, 2015
Priority date	Sep 5, 2014
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

A semiconductor device includes a substrate having a first part and a second part, the first and second parts being continuous with each other and at different height levels, a first semiconductor chip overlapping the first and second parts of the substrate, an electrical interconnection structure connecting the first part of the substrate and the first semiconductor chip, a distance between the first part of the substrate and the first semiconductor chip being shorter than a distance between the second part of the substrate and the first semiconductor chip, and at least one electronic component in a space between the second part of the substrate and the first semiconductor chip.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate having a first part, a second part, and an inclined part between the first and second parts, the first and second parts being at different height levels, and the inclined part connecting the first part to the second part, and being continuous with each of the first and second parts;
a first semiconductor chip overlapping the first part through a central part of the first semiconductor chip, and overlapping the second part and the inclined part;
an electrical interconnection structure connecting the first part of the substrate and the first semiconductor chip, a distance between the first part of the substrate and the first semiconductor chip being shorter than a distance between the second part of the substrate and the first semiconductor chip; and
at least one electronic component in a space between the second part of the substrate and the first semiconductor chip.

2. The semiconductor device as claimed in claim 1 , wherein a bottom surface of the first semiconductor chip overlaps a top of the at least one electronic component.

3. The semiconductor device as claimed in claim 1 , wherein the first semiconductor chip extends beyond the at least one electronic component along a direction oriented from the first part of the substrate toward the second part of the substrate.

4. The semiconductor device as claimed in claim 1 , wherein each of the substrate and the first semiconductor chip completely overlaps the at least one electronic component.

5. The semiconductor device as claimed in claim 1 , wherein a distance between a bottom surface of the first semiconductor chip and a top surface of the second part of the substrate along a normal direction to the substrate is larger than a height of the at least one electronic component as measured from an upper surface of the substrate.

6. The semiconductor device as claimed in claim 1 , wherein the at least one electronic component is electrically connected to the substrate.

7. The semiconductor device as claimed in claim 6 , wherein the at least one electronic component is a passive electronic component.

8. The semiconductor device as claimed in claim 6 , wherein the at least one electronic component is a driver chip or a controller chip.

9. The semiconductor device as claimed in claim 1 , wherein the electrical interconnection structure is a flip-chip interconnection contacting a bottom surface of a center part of the first semiconductor chip and the first part of the substrate.

10. The semiconductor device as claimed in claim 1 , further comprising a mold layer between the second part of the substrate and the first semiconductor chip, the at least one electronic component being embedded in the mold layer between the second part of the substrate and the first semiconductor chip.

11. The semiconductor device as claimed in claim 1 , wherein the second part of the substrate is connected to a lower substrate with a lower semiconductor chip thereon, the lower substrate and the at least one electronic component being on opposite surfaces of the second part of the substrate.

12. The semiconductor device as claimed in claim 11 , wherein:
a distance between a lower surface of the first semiconductor chip and an upper surface of the lower substrate along a normal direction to the substrate is constant, and
a distance between the first part of the substrate and the lower substrate is longer than a distance between the second part of the substrate and the lower substrate.

13. The semiconductor device as claimed in claim 1 , wherein:
the second and inclined parts surround the first part, and
the space between the second part of the substrate and the first semiconductor chip surrounds the first part of the substrate.

14. The semiconductor device as claimed in claim 13 , wherein the space surrounding the first part of the substrate has a constant height, a plurality of electronic components spaced apart from each other being positioned in the space around the first part.

15. A semiconductor package, comprising:
a lower semiconductor chip on a lower substrate;
an upper substrate over the lower substrate, the upper substrate having a first part, a second part, and an inclined part between the first and second parts, the first and second parts being at different height levels, and the inclined part connecting the first part to the second part, and being continuous with each of the first and second parts;
an upper semiconductor chip on the upper substrate;
a first electrical interconnection structure connecting the first part of the upper substrate and the upper semiconductor chip
a second electrical interconnection structure connecting the second part of the upper substrate to the lower substrate; and
at least one electronic component on the second part of the upper substrate,
wherein the second part of the upper substrate has an upper surface located closer to the lower substrate than an upper surface of the first part of the upper substrate,
wherein the lower semiconductor chip is between the lower substrate and the first part of the upper substrate, and
wherein the lower semiconductor chip does not overlap the second part of the upper substrate.

16. A semiconductor package, comprising:
a lower semiconductor chip on a lower substrate;
an upper substrate over the lower substrate, the upper substrate having a first part, a second part, and an inclined part between the first and second parts, the first and second parts being at different height levels, and the inclined part connecting the first part to the second part, and being continuous with each of the first and second parts;
an upper semiconductor chip overlapping the first part through a central part of the first semiconductor chip, and overlapping the second part and the inclined part;
a first electrical interconnection structure connecting the first part of the upper substrate and the upper semiconductor chip, a distance between the first part of the upper substrate and the upper semiconductor chip being shorter than a distance between the second part of the upper substrate and the upper semiconductor chip;
a second electrical interconnection structure connecting the second part of the upper substrate to the lower substrate, the upper semiconductor chip overlapping at least part of the second electrical interconnection structure; and
a space between an upper surface of the second part of the upper substrate and a bottom surface of a peripheral part of the upper semiconductor chip,
wherein the first part and the inclined part of the upper substrate define a recess relative to a bottom surface of the second part of the upper substrate, the recess facing the lower substrate, and the lower semiconductor chip extending into the recess to overlap the center of the first semiconductor chip.

17. The semiconductor package as claimed in claim 16 , wherein the space has a constant height.

18. The semiconductor package as claimed in claim 17 , further comprising an electronic component in the space, the electronic component being electrically connected to the upper substrate.

19. The semiconductor package as claimed in claim 15 , wherein:
the upper semiconductor chip overlaps the first part, the inclined part, and the second part of the upper substrate, and
the at least one electronic component is between the second part of the upper substrate and the upper semiconductor chip.

Assignees

• Lee Baik-Woo
• Lee Seok-Hyun
• Samsung Electronics Co Ltd

Inventors

• Lee Baik-Woo
• Lee Seok-Hyun

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title