Semiconductor package and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9640513-B2
Application number	US-201514682113-A
Country	US
Kind code	B2
Filing date	Apr 9, 2015
Priority date	Jul 1, 2014
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a first package having a first package substrate mounted with a lower semiconductor chip, and a second package having a second package substrate mounted with upper semiconductor chips. The second package substrate includes a chip region on which the upper semiconductor chips are mounted, and a connection region provided therearound. The chip region includes a first surface defining a first recess region and a second surface defining a first protruding portion. The upper semiconductor chips are mounted on opposite edges of the second surface and spaced apart from each other to have portions protruding toward the connection region beyond the chip region.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a first package including a first package substrate on which a lower semiconductor chip is mounted;
a second package stacked on the first package, the second package including a second package substrate on which upper semiconductor chips are mounted; and
an interposer disposed between the first package and the second package,
wherein the second package substrate comprises:
a chip region overlapped with the lower semiconductor chip to provide a region on which the upper semiconductor chips are mounted; and
a connection region provided around the chip region,

wherein the chip region comprises a first surface that faces the lower semiconductor chip and forms a first recess region and a second surface that is opposite to the first surface and forms a first protruding portion,
wherein the upper semiconductor chips are mounted on opposite edges of the second surface and spaced apart from each other to have portions protruding toward the connection region beyond the chip region, and
wherein each of the upper semiconductor chips extends beyond the respective edge of the second surface.

2. The semiconductor package of claim 1 , wherein the lower semiconductor chip is provided in such a way that an upper or entire portion thereof is inserted into the first recess region.

3. The semiconductor package of claim 1 , further comprising bonding wires connecting the upper semiconductor chips electrically to the chip region of the second package substrate.

4. The semiconductor package of claim 3 , wherein the chip region of the second package substrate comprises a center region positioned between the upper semiconductor chips, and the bonding wires are provided on the center region.

5. The semiconductor package of claim 1 , further comprising connecting elements connecting the connection region of the second package substrate electrically to the first package substrate.

6. The semiconductor package of claim 1 , further comprising:
first connecting elements connecting the first package substrate electrically to the interposer; and
second connecting elements connecting the connection region of the second package substrate electrically to the interposer,
wherein the first connecting elements are provided on an edge region of the interposer that is overlapped with the connection region, when viewed in plan view.

7. The semiconductor package of claim 6 , wherein the interposer comprises third and fourth surfaces that are opposite to each other, the third surface is formed to face the lower semiconductor chip and define a second recess region on the chip region, and the fourth surface is formed to have a second protruding portion.

8. The semiconductor package of claim 7 , further comprising a mold layer provided to cover the fourth surface of the interposer and enclose the second connecting elements.

9. The semiconductor package of claim 1 , wherein the second package substrate is provided in such a way that the chip region protrudes toward a direction away from the lower semiconductor chip with respect to the connection region.

10. A semiconductor package, comprising:
a first package including a first package substrate on which a lower semiconductor chip is mounted; and
a second package stacked on the first package, the second package including a second package substrate on which upper semiconductor chips are mounted,
wherein the second package substrate comprises:
a chip region overlapped with the lower semiconductor chip to provide a region on which the upper semiconductor chips are mounted; and
a connection region provided around the chip region,

wherein the chip region comprises a first surface that faces the lower semiconductor chip and forms a first recess region and a second surface that is opposite to the first surface and forms a first protruding portion,
wherein the upper semiconductor chips are mounted on opposite edges of the second surface and spaced apart from each other to have portions protruding toward the connection region beyond the chip region,
wherein each of the upper semiconductor chips extends beyond the respective edge of the second surface, and
wherein the semiconductor package further comprising a heat-transfer layer provided between the lower semiconductor chip and the first surface of the second package substrate.

11. A method of fabricating a semiconductor package, the method comprising:
preparing a first package substrate on which a lower semiconductor chip is mounted;
preparing a second package substrate on which first and second upper semiconductor chips are mounted, the second package substrate having first and second surfaces, which are opposite to each other and define a recess region and a protruding portion, respectively, and having a chip region overlapped with the lower semiconductor chip and a connection region adjacent to the chip region; and
mounting the second package substrate on the first package substrate in such a way that the lower semiconductor chip faces the recess region,
wherein the first and second upper semiconductor chips are mounted on opposite edges of the second surface of the second package substrate and spaced apart from each other to have portions protruding toward the connection region beyond the chip region of the second package substrate,
wherein each of the first and second upper semiconductor chips extends beyond the respective edge of the second surface, and
wherein the preparing of the second package substrate comprises:
preparing a first mold having a protruding central region and a second mold having a recessed central region;
disposing the second package substrate between the first and second molds;
applying pressure to the second package substrate through the first and second molds;
separating the second package substrate from the first and second molds;
mounting the first and second upper semiconductor chips on the second package substrate; and
forming a mold layer on the second package substrate.

12. The method of claim 11 , wherein the preparing of the first package substrate comprises:
disposing the lower semiconductor chip on the first package substrate; and
forming an under-fill resin layer to fill a space between the lower semiconductor chip and the first package substrate.

13. A method of fabricating a semiconductor package, the method comprising:
preparing a first package substrate on which a lower semiconductor chip is mounted;
preparing a second package substrate on which first and second upper semiconductor chips are mounted, the second package substrate having first and second surfaces, which are opposite to each other and define a recess region and a protruding portion, respectively, and having a chip region overlapped with the lower semiconductor chip and a connection region adjacent to the chip region; and
mounting the second package substrate on the first package substrate in such a way that the lower semiconductor chip faces the recess region,
wherein the first and second upper semiconductor chips are mounted on opposite edges of the second surface of the second package substrate and spaced apart from each other to have portions protruding toward the connection region beyond the chip region of the second package substrate,
wherein each of the first and second upper semiconductor chips extends beyond the respective edge of the second surface, and
wherein the preparing of the second package substrate comprises:
mounting the first and second upper semiconductor chip on the second package substrate;
preparing a first mold having a protruding central region and a second mold havi

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Seokhyun
• Jang Chul-Yong
• Lee Jongho

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title