Method for growing III-V compound semiconductor thin films on silicon-on-insulators

Patent metadata

Field	Value
Publication number	US-11742203-B2
Application number	US-202016801224-A
Country	US
Kind code	B2
Filing date	Feb 26, 2020
Priority date	Feb 26, 2020
Publication date	Aug 29, 2023
Grant date	Aug 29, 2023

Abstract

The present disclosure relates to a method for growing III-V compound semiconductors on silicon-on-insulators. Starting from {111}-oriented Si seed surfaces between a buried oxide layer and a patterned mask layer, the III-V compound semiconductor is grown within lateral trenches by metal organic chemical vapor deposition such that the non-defective portion of the III-V compound semiconductor formed on the buried oxide layer is substantially free of crystalline defects and has high crystalline quality.

First claim

What is claimed is:

1. A method for forming a III-V compound semiconductor thin film on a buried oxide layer of silicon-on-insulator comprising:
providing a layered (001)-oriented silicon-on-insulator substrate comprising a silicon (Si) device layer, the buried oxide layer, and a patterned mask layer, the Si device layer being sandwiched between the buried oxide layer and the patterned mask layer, the patterned mask layer comprising one or more vertical trenches formed in the patterned mask layer and located on the Si device layer such that one or more exposed Si surfaces are formed on the Si device layer;
starting from each exposed Si surface, anisotropic-etching the Si device layer laterally thereby forming one or more lateral trenches between the buried oxide layer and the patterned mask layer;
etching each lateral Si surface of each lateral trench by anisotropic wet etching thereby forming one or more {111}-oriented Si seed surfaces between the buried oxide layer and the patterned mask layer; and
starting from each {111}-oriented Si seed surface, growing an epitaxial layer of the III-V compound semiconductor thin film laterally within a respective lateral trench by metal organic chemical vapor deposition thereby forming one or more epitaxial layers between the buried oxide layer and the patterned mask layer such that each epitaxial layer has a non-defective portion and a defective portion, the defective portion being sandwiched between the {111}-oriented Si seed surface and the non-defective portion, the non-defective portion forming the III-V compound semiconductor thin film on the buried oxide layer,
said forming the one or more epitaxial layers between the buried oxide layer and the patterned mask layer comprising:
starting from each {111}-oriented Si seed surface, growing a nucleation layer of the III-V compound semiconductor thin film laterally within the respective lateral trench at a first growth temperature, said nucleation layer consisting of multiple nucleation sites;
starting from each nucleation layer, growing a main layer of the III-V compound semiconductor thin film laterally within the respective lateral trench at a second growth temperature such that each epitaxial layer comprises the nucleation layer and the main layer, the nucleation layer being sandwiched between the {111}-oriented Si seed surface and the main layer;
said nucleation layer and main layer having the same growth front direction such that planar disorders including stacking faults generated due to lattice mismatch between the III-V compound semiconductor thin film and the {111}-oriented Si seed surface either are trapped right at an interface between the nucleation layer and the {111}-oriented Si seed surface or propagate into the main layer of the epitaxial layer in the {111} direction and then terminate at the buried oxide layers;
said nucleation layer and main layer being grown by metal organic chemical vapor deposition (MOCVD); and
said nucleation layer being grown under a higher V/III ratio but a lower growth temperature than those for growing said main layer.

2. The method of claim 1 , wherein the defective portion has a width between 1.3d and 1.5d, d being a thickness of the Si device layer.

3. The method of claim 1 , wherein the III-V compound semiconductor thin film is indium phosphide (InP), gallium arsenide (GaAs), gallium antimonide (GaSb), Indium arsenide (InAs), a ternary alloy thereof, or a quaternary alloy thereof.

4. The method of claim 1 , wherein the Si device layer has a thickness between 1 nm and 1000 nm.

5. The method of claim 1 , wherein the buried oxide layer comprises SiO 2 layer and has a thickness between 1 nm and 2000 nm.

6. The method of claim 1 , wherein the patterned mask layer comprises SiO 2 , SiN or Al 2 O 3 ; and each vertical trench has a width between 1 nm and 100 μm.

7. The method of claim 1 , wherein the patterned mask layer is a patterned top oxide layer having a thickness between 1 nm and 1000 nm.

8. The method of claim 1 , wherein the anisotropic wet etching comprises potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH).

9. The method of claim 1 , wherein the first growth temperature is between 350° C. and 450° C.; and the second growth temperature is between 450° C. and 750° C.

10. The method of claim 1 further comprising:
removing the patterned mask layer after the step of growing the one or more epitaxial layers; and
removing the defective portion of each epitaxial layer.

11. The method of claim 1 , wherein the layered (001)-oriented silicon-on-insulator (SOI) substrate is prepared by the steps of:
providing the layered (001)-oriented silicon-on-insulator (SOI) substrate comprising the Si device layer, the buried oxide layer and a Si handle layer, the buried oxide layer being sandwiched by the Si device layer and the Si handle layer;
oxidizing a top surface of the Si device layer thereby forming a mask layer on the Si device layer; and
patterning and etching the mask layer thereby forming the patterned mask layer.

12. A method for growing a III-V compound semiconductor thin film on a buried oxide layer of silicon-on-insulator comprising:
providing a layered (001)-oriented silicon-on-insulator substrate comprising a Si device layer, the buried oxide layer, and a patterned mask layer, the Si device layer being sandwiched between the buried oxide layer and the patterned mask layer, the patterned mask layer comprising one or more vertical trenches formed in the patterned mask layer and located on the Si device layer such that one or more exposed Si surfaces are formed on the Si device layer;
starting from each exposed Si surface, anisotropic-etching the Si device layer laterally thereby forming one or more lateral trenches between the buried oxide layer and the patterned mask layer;
etching each lateral Si surface of each lateral trench by anisotropic wet etching thereby forming one or more {111}-oriented Si seed surfaces between the buried oxide layer and the patterned mask layer;
growing a wetting layer laterally on each lateral Si surface by first metal organic chemical vapor deposition; and
starting from each wetting layer, growing an epitaxial layer of the III-V compound semiconductor thin film laterally within a respective lateral trench by second metal organic chemical vapor deposition thereby forming one or more epitaxial layers between the buried oxide layer and the patterned mask layer such that each epitaxial layer has a non-defective portion and a defective portion, the defective portion being sandwiched between the {111}-oriented Si surface and the non-defective portion, the non-defective portion forming the region of the III-V compound semiconductor thin film on the buried oxide layer,
said forming the one or more epitaxial layers comprises:
starting from each wetting layer, growing a nucleation layer of the III-V compound semiconductor thin film laterally within the respective lateral trench at a first growth temperature, said nucleation layer consisting of multiple nucleation sites; and
starting from each nucleation layer, growing a main layer of the III-V compound semiconductor thin film laterally within the respective lateral trench at a second growth temperature such that each epitaxial layer comprises the nucleation layer and the main layer, the nucleation layer being sandwiched between the wetting layer and the main layer;
said nucleation layer and main layer having the same growth front direction such that planar disorders including stacking faults generated due to lattice mismatch between the III-V compound semiconductor thin film and the {111}-oriented Si seed surface either are trapped right at

Assignees

• Univ Hong Kong Science & Tech

Inventors

• Lau Kei May
• Han Yu

Classifications

• H10P50/644

  Anisotropic liquid etching (H10P50/61 takes precedence) · CPC title

• H10P14/3421

  Arsenides · CPC title

• H10P14/3418

  Phosphides · CPC title

• H10P14/2922

  being non-crystalline insulating materials, e.g. glass or polymers · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title