Reduction of edge effects from aspect ratio trapping

Patent metadata

Field	Value
Publication number	US-9356103-B2
Application number	US-201514629731-A
Country	US
Kind code	B2
Filing date	Feb 24, 2015
Priority date	Jul 1, 2008
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A device includes a crystalline material within an area confined by an insulator. In one embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique. Method and apparatus embodiments of the invention can reduce edge effects in semiconductor devices. Embodiments of the invention can provide a planar surface over a buffer layer between a plurality of uncoalesced ART structures.

First claim

What is claimed is:

1. A method comprising:
forming a first crystalline material in and extending out of an opening, the opening being defined by a dielectric layer on a substrate, the substrate comprising a second crystalline material, the first crystalline material being lattice mismatched to the second crystalline material;
forming a third material over and lateral adjoining a lateral edge of the first crystalline material, the third material being more defective than the first crystalline material;
planarizing the third material and the first crystalline material to form a planar surface; and
forming a device in and/or above the first crystalline material while the third material is more defective than the first crystalline material.

2. The method of claim 1 , wherein defects arising from the lattice mismatch within the first crystalline material terminate at a sidewall of the opening.

3. The method of claim 1 , wherein the first crystalline material and the third material are different materials.

4. The method of claim 1 , wherein the third material is amorphous.

5. The method of claim 1 , wherein the third material is polycrystalline.

6. The method of claim 1 further comprising forming a planar device layer over the planar surface, the device being formed at least partially in the planar device layer.

7. A method comprising:
forming a first crystalline material extending above an opening, the opening being defined by a dielectric layer on a substrate, the substrate comprising a second crystalline material, the first crystalline material being lattice mismatched to the second crystalline material;
forming a third material laterally adjoining a lateral edge of the first crystalline material, the third material having a material composition different from the first crystalline material;
planarizing the third material and the first crystalline material to form a planar surface; and
forming a device in and/or above the first crystalline material.

8. The method of claim 7 , wherein the first crystalline material is further formed in the opening, defects arising from the lattice mismatch within the first crystalline material terminating at a sidewall of the opening.

9. The method of claim 7 , wherein the third material is more defective than the first crystalline material.

10. The method of claim 7 , wherein the third material is amorphous.

11. The method of claim 7 , wherein the third material is polycrystalline.

12. The method of claim 7 , wherein the forming the third material comprises epitaxially growing the third material.

13. The method of claim 7 further comprising forming a planar device layer over the planar surface, the device being formed at least partially in the planar device layer.

14. A method comprising:
forming a first crystalline material extending above an opening, the opening being defined by a dielectric layer on a substrate, the substrate comprising a second crystalline material, the first crystalline material being lattice mismatched to the second crystalline material;
after forming the first crystalline material, forming a third material contacting a lateral edge of the first crystalline material, the third material being (i) more defective than the first crystalline material, (ii) a different material composition from the first crystalline material, and/or (iii) a combination thereof;
planarizing the third material and the first crystalline material to form a planar surface; and
forming a device in and/or above the first crystalline material.

15. The method of claim 14 , wherein the first crystalline material is further formed in the opening, defects arising from the lattice mismatch within the first crystalline material terminating at a sidewall of the opening.

16. The method of claim 14 , wherein the third material is more defective than the first crystalline material.

17. The method of claim 16 , wherein the third material is amorphous.

18. The method of claim 16 , wherein the third material is polycrystalline.

19. The method of claim 14 , wherein the forming the third material comprises a crystalline material with a different material composition from the first crystalline material.

20. The method of claim 14 further comprising forming a planar device layer over the planar surface, the device being formed at least partially in the planar device layer.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Cheng Zhiyuan

Classifications

• H10P14/2901

  Materials · CPC title

• H10P14/3411 Primary

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3256

  Microstructure · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H10P14/271

  characterised by the preparation of substrate for selective deposition · CPC title