Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods

Patent metadata

Field	Value
Publication number	US-9064699-B2
Application number	US-201414258704-A
Country	US
Kind code	B2
Filing date	Apr 22, 2014
Priority date	Sep 30, 2013
Publication date	Jun 23, 2015
Grant date	Jun 23, 2015

Abstract

Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods are provided. The methods may include forming an oxide layer on a substrate and forming a recess in the oxide layer and the substrate. The methods may further include forming an epitaxially grown semiconductor pattern in the recess that contacts a sidewall of the substrate at an interface between the oxide layer and the substrate and defines an upper surface of a void in the recess in the substrate.

First claim

What is claimed is:

1. A method of forming a semiconductor pattern, the method comprising:
forming an oxide layer on a substrate;
forming a recess in the oxide layer and the substrate; and
forming an epitaxially grown semiconductor pattern in the recess, which contacts a sidewall of the substrate at an interface between the oxide layer and the substrate and defines an upper surface of a void in the recess in the substrate.

2. The method of claim 1 , wherein forming the recess comprises forming a lower portion of the recess in the substrate having an aspect ratio greater than 3 such that the void exposes the sidewall of the substrate.

3. The method of claim 1 , wherein forming the recess comprises forming an upper portion of the recess through the oxide layer having an aspect ratio greater than 1.

4. The method of claim 1 , further comprising:
implanting oxygen ions into the substrate to form an insulating region under the recess.

5. The method of claim 1 , further comprising:
widening a portion of the recess in the substrate at the interface of the substrate and the oxide layer to form an undercut region.

6. The method of claim 1 , wherein forming the epitaxially grown semiconductor pattern comprises:
epitaxially growing a lower semiconductor pattern defining the upper surface of the void in the recess in the substrate using the sidewall of the substrate at the interface between the oxide layer and the substrate as a first seed layer; and
epitaxially growing an upper semiconductor pattern in the recess using the lower semiconductor pattern as a second seed layer.

7. The method of claim 6 , wherein the void exposes the sidewall of the substrate.

8. The method of claim 6 , wherein the lower semiconductor pattern comprises a material different from the upper semiconductor pattern.

9. The method of claim 8 , wherein the lower semiconductor pattern comprises silicon germanium (SiGe), and the upper semiconductor pattern comprises germanium (Ge).

10. The method of claim 1 , wherein:
the substrate comprises a first semiconductor layer and a second semiconductor layer extending between the oxide layer and the first semiconductor layer;
the second semiconductor layer comprises germanium (Ge), silicon germanium (SiGe), indium gallium arsenide (InGaAs), or a III-V compound; and
the epitaxially grown semiconductor pattern contacts a sidewall of the second semiconductor layer.

11. The method of claim 10 , wherein a thickness of the second semiconductor layer is in a range of about 100 nm to about 1 μm.

12. A method of forming a fin-shaped semiconductor pattern, the method comprising:
forming an oxide layer on a substrate;
forming a recess through the oxide layer and in the substrate;
performing a first epitaxial growth process to form an overhang seed layer in the recess using a sidewall of the substrate at an interface between the oxide layer and the substrate as a first seed layer, the overhang seed layer defining an upper surface of a void in the recess;
performing a second epitaxial growth process to form a semiconductor pattern in the recess using the overhang seed layer as a second seed layer; and
recessing the oxide layer to form the fin-shaped semiconductor pattern by exposing an upper portion of the semiconductor pattern.

13. The method of claim 12 , wherein:
performing the first epitaxial growth process further comprises forming a bottom seed pattern on a bottom of the recess; and
the overhang seed layer is isolated from the bottom seed pattern.

14. The method of claim 12 , wherein:
the substrate comprises a first semiconductor layer and a second semiconductor layer extending between the oxide layer and the first semiconductor layer, the second semiconductor layer comprising germanium (Ge), silicon germanium (SiGe), indium gallium arsenide (InGaAs), or a III-V compound; and
the recess exposes a sidewall of the second semiconductor layer comprising the first seed layer.

15. The method of claim 14 , wherein a thickness of the second semiconductor layer is in a range of about 100 nm to about 1 μm.

16. A method of forming a semiconductor layer, the method comprising:
sequentially forming a semiconductor seed layer and an oxide layer on the substrate;
forming a plurality of recesses in the oxide layer and the semiconductor seed layer;
epitaxially growing a plurality of semiconductor patterns in the respective plurality of recesses using portions of sidewalls of the semiconductor seed layer at an interface between the oxide layer and the semiconductor seed layer as seed layers until upper portions of the plurality of semiconductor patterns protrude from the respective plurality of recesses, the plurality of semiconductor patterns defining upper surfaces of a plurality of voids in the respective plurality of recesses; and
epitaxially growing the semiconductor layer extending on the oxide layer using the plurality of semiconductor patterns as seed layers.

17. The method of claim 16 , wherein:
forming the plurality of recesses comprises forming lower portions of the plurality of recesses in the semiconductor seed layer; and
each of the lower portions of the plurality of recesses has an aspect ratio greater than 3 such that the each of the plurality of voids exposes the sidewalls of the semiconductor seed layer.

18. The method of claim 16 , wherein a thickness of the semiconductor seed layer is in a range of about 100 nm to about 1 μm.

19. The method of claim 16 , wherein epitaxially growing the plurality of semiconductor patterns comprises:
epitaxially growing a plurality of lower semiconductor patterns defining the upper surfaces of the respective plurality of voids using the portions of sidewalls of the semiconductor seed layer at the interface between the oxide layer and the semiconductor seed layer as the seed layers; and
epitaxially growing a plurality of upper semiconductor patterns in the respective plurality of recesses from the respective plurality of lower semiconductor patterns.

20. The method of claim 19 , wherein:
epitaxially growing the plurality of upper semiconductor patterns comprises growing the plurality of upper semiconductor patterns protruding from the respective plurality of recesses; and
epitaxially growing the semiconductor layer comprises laterally growing the plurality of upper semiconductor patterns until adjacent ones of the plurality of upper semiconductor patterns contact each other.

Assignees

• Wang Wei-E
• Rodder Mark S
• Bowen Robert C
• Samsung Electronics Co Ltd

Inventors

• Wang Wei-E
• Rodder Mark S
• Bowen Robert C

Classifications

• H10P14/3421

  Arsenides · CPC title

• H10P14/3414

  being group IIIA-VIA materials · CPC title

• H10P14/3411 Primary

  Silicon, silicon germanium or germanium · CPC title

• H10P14/276

  Lateral overgrowth · CPC title

• H10P14/271

  characterised by the preparation of substrate for selective deposition · CPC title