Controlled confined lateral III-V epitaxy

Patent metadata

Field	Value
Publication number	US-9748098-B2
Application number	US-201615237114-A
Country	US
Kind code	B2
Filing date	Aug 15, 2016
Priority date	Dec 30, 2015
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

After forming a seed layer over a first end of a sacrificial semiconductor layer composed of silicon germanium, a remaining portion of the sacrificial semiconductor layer is removed to provide a trench. Next, a semiconductor barrier layer is formed on a sidewall of the seed layer that is exposed by the trench. A III-V compound semiconductor layer is formed within the trench by a lateral epitaxial semiconductor regrowth process.

First claim

What is claimed is:

1. A method of forming a semiconductor structure comprising:
forming dielectric material layer over a sacrificial semiconductor layer that is located over a region of an insulator layer, wherein the sacrificial semiconductor layer comprises silicon-germanium having a high germanium concentration;
forming a first trench opening extending through the dielectric material layer and the sacrificial semiconductor layer, wherein the first trench opening exposes a first sidewall of the sacrificial semiconductor layer;
forming a seed layer over the first sidewall of the sacrificial semiconductor layer;
forming a second trench opening extending through the dielectric material layer and the sacrificial semiconductor layer, wherein the second trench opening exposes a second sidewall of the sacrificial semiconductor layer opposite to the first sidewall;
removing the sacrificial semiconductor layer to provide a trench, wherein the trench exposes a sidewall surface of the seed layer;
growing a III-V compound semiconductor material within the trench and laterally outwards from the sidewall surface of the seed layer to provide a III-V compound semiconductor layer; and
removing a defect-containing region of the III-V compound semiconductor layer.

2. The method of claim 1 , wherein the germanium concentration is greater than 35%.

3. The method of claim 2 , wherein the germanium concentration is from 50% to 70%.

4. The method of claim 1 , wherein the seed layer comprises silicon.

5. The method of claim 1 , wherein the defect-containing region is removed by an anisotropic etch.

6. The method of claim 5 , wherein the anisotropic etch also removes the seed layer.

7. The method of claim 1 , wherein the sacrificial semiconductor layer is removed by a lateral etch, and wherein the lateral etch comprises hydrogen peroxide or gaseous HCl.

8. The method of claim 1 , wherein the growing the III-V compound semiconductor material comprises an aspect ratio trapping process, and wherein the defect-containing region is formed adjacent the sidewall surface of the seed layer.

9. The method of claim 8 , wherein the growing the III-V compound semiconductor material is performed by a selective epitaxial growth.

10. The method of claim 1 , further comprising forming a dielectric liner over a top surface and sidewall surfaces of the sacrificial semiconductor layer prior to the forming the dielectric material layer, wherein each of the first trench opening and the second trench opening also extends through the dielectric liner.

11. The method of claim 10 , further comprising removing the dielectric material layer and the dielectric liner after the removing the defect-containing region.

12. The method of claim 1 , wherein the forming the first trench opening comprises:
forming a first mask layer over the dielectric material layer;
patterning the first mask layer to provide a first opening extending through the first mask layer, wherein the first opening exposes a first end of the sacrificial semiconductor layer; and
removing portions of the dielectric material layer and the sacrificial semiconductor layer that are exposed by the first opening to provide the first trench opening.

13. The method of claim 12 , further comprising removing the first mask layer after the forming the seed layer.

14. The method of claim 1 , wherein the forming the second trench opening comprises:
forming a second mask layer over the dielectric material layer, the seed layer and the insulator layer, wherein the second mask layer completely fills the first trench opening;
patterning the second mask layer to provide a second opening extending through the second mask layer, wherein the second opening exposes a second end of the sacrificial semiconductor layer opposite to the first end; and
removing portions of the dielectric material layer and the sacrificial semiconductor layer that are exposed by the second opening to provide the second trench opening.

15. The method of claim 14 , further comprising removing the second mask layer after the removing the sacrificial semiconductor layer.

16. The method of claim 1 , further comprising providing a semiconductor layer over another region of the insulator layer, wherein the semiconductor layer comprises silicon, germanium, or silicon germanium, and the another region is masked by the dielectric material layer.

17. The method of claim 16 , further comprising forming another dielectric liner over a top surface and sidewall surface of the semiconductor layer prior to the forming the dielectric material layer.

18. The method of claim 1 , wherein the insulator layer is formed on a handle substrate.

19. The method of claim 1 , wherein the dielectric material layer comprises a dielectric oxide.

20. The method of claim 1 , wherein the III-V compound semiconductor layer has the same crystal orientation as the sidewall surface of the seed layer.

Assignees

• IBM

Inventors

• Balakrishnan Karthik
• Czornomaz Lukas
• Hashemi Pouya
• Reznicek Alexander

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/646

  of Group III-V materials · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P36/00

  Gettering within semiconductor bodies · CPC title