Stacked nanowire devices formed using lateral aspect ratio trapping

Patent metadata

Field	Value
Publication number	US-9917179-B2
Application number	US-201615220723-A
Country	US
Kind code	B2
Filing date	Jul 27, 2016
Priority date	Sep 29, 2015
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A method for manufacturing a semiconductor device comprises depositing alternating layers of a plurality of first dielectric layers and a plurality of second dielectric layers on a substrate in a stacked configuration, forming one or more first openings in the stacked configuration to a depth penetrating below an upper surface of a bottom second dielectric layer of the plurality of second dielectric layers, forming one or more second openings in the stacked configuration to a depth corresponding to an upper surface of the substrate or below an upper surface of the substrate, removing the plurality of second dielectric layers from the stacked configuration to form a plurality of gaps, and epitaxially growing a semiconductor material from a seed layer in the one or more second openings to fill the one or more first and second openings and the plurality of gaps, wherein defects caused by a lattice mismatch between the epitaxially grown semiconductor material and a material of the substrate are contained at a bottom portion of the one or more second openings.

First claim

We claim:

1. A semiconductor device, comprising:
a substrate;
a plurality of nanowires on the substrate in a stacked configuration, wherein the nanowires comprise a material having a lattice mismatch with a material of the substrate and are free of dislocation defects;
a gate structure formed on the stacked configuration; and
at least one opening in the substrate apart from the stacked configuration, wherein the opening is filled with the material having the lattice mismatch, and containing defects caused by the lattice mismatch.

2. The semiconductor device of claim 1 , wherein the material of the substrate comprises silicon and the material of the nanowires comprises one of a III-V compound, a II-VI compound and germanium.

3. The semiconductor device of claim 1 , wherein a bottom of the opening is formed in a V-shape.

4. The semiconductor device of claim 1 , wherein a top of the opening is at a top surface of the substrate.

5. The semiconductor device of claim 1 , wherein a width of the opening is about 10 nm-about 25 nm.

6. The semiconductor device of claim 1 , wherein the material of the substrate comprises silicon and the material of the nanowires and in the opening comprises one of a III-V compound, a II-VI compound and germanium.

7. The semiconductor device of claim 1 , wherein gate structure comprises a metal formed on a high-K dielectric.

8. A semiconductor device, comprising:
a substrate;
a plurality of channel layers on the substrate in a stacked configuration, wherein the channel layers comprise a semiconductor material having a lattice mismatch with a semiconductor material of the substrate and are free of dislocation defects;
a gate structure formed on the stacked configuration; and
at least one opening in the substrate apart from the stacked configuration, wherein the opening is filled with the semiconductor material having the lattice mismatch, and containing defects caused by the lattice mismatch.

9. The semiconductor device of claim 8 , wherein the semiconductor material of the substrate comprises silicon and the semiconductor material of the channel layers comprises one of a III-V compound, a II-VI compound and germanium.

10. The semiconductor device of claim 8 , wherein a bottom of the opening is formed in a V-shape.

11. The semiconductor device of claim 8 , wherein a top of the opening is at a top surface of the substrate.

12. The semiconductor device of claim 8 , wherein a width of the opening is about 10 nm-about 25 nm.

13. The semiconductor device of claim 8 , wherein the semiconductor material of the substrate comprises silicon and the semiconductor material of the channel layers and in the opening comprises one of a III-V compound, a II-VI compound and germanium.

14. The semiconductor device of claim 8 , wherein gate structure comprises a metal formed on a high-K dielectric.

Assignees

• IBM

Inventors

• Balakrishnan Karthik
• Cheng Kangguo
• Hashemi Pouya
• Reznicek Alexander

Classifications

• H10P14/3424

  being Group IIB-VIA materials · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10P14/3414

  being group IIIA-VIA materials · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title