Dynamic adjustment of data integrity operations of a memory system based on error rate classification

Patent metadata

Field	Value
Publication number	US-11740970-B2
Application number	US-202016807056-A
Country	US
Kind code	B2
Filing date	Mar 2, 2020
Priority date	Mar 2, 2020
Publication date	Aug 29, 2023
Grant date	Aug 29, 2023

Abstract

A memory sub-system configured to dynamically select an option to process encoded data retrieved from memory cells of a memory component, based on a prediction generated using signal and noise characteristics of memory cells storing the encoded data. For example, the memory component is enclosed in an integrated circuit and has a calibration circuit. The signal and noise characteristics are measured by the calibration circuit as a byproduct of executing a read command in the memory component to retrieve the encoded data. A data integrity classifier configured in the memory sub-system generates a prediction based on the signal and noise characteristics. Based on the prediction, the memory sub-system selects an option from a plurality of options configured in the memory sub-system to process the encoded data.

First claim

What is claimed is:

1. A memory sub-system, comprising:
a processing device; and
at least one memory component, the memory component being enclosed in an integrated circuit package, the memory component having:
a group of memory cells formed on an integrated circuit die; and
a calibration circuit;

wherein the processing device is configured to transmit a command to the memory component to retrieve data from an address;
wherein in response to the command and during execution of the command, the calibration circuit is configured to measure signal and noise characteristics of the group of memory cells associated with encoded data retrieved from the group of memory cells;
wherein the memory sub-system has a data integrity classifier and a plurality of options available to process the encoded data;
wherein the data integrity classifier is configured to generate a prediction based on the signal and noise characteristics, wherein the prediction comprises a predicted error rate for decoding the encoded data retrieved during execution of the command; and
wherein the memory sub-system is configured to select an option from the plurality of options based on the prediction and decode the encoded data using the selected option.

2. The memory sub-system of claim 1 , wherein the calibration circuit is formed at least in part on the integrated circuit die.

3. The memory sub-system of claim 2 , wherein the signal and noise characteristics include statistic data of memory cells at varying operating parameters.

4. The memory sub-system of claim 3 , wherein the varying operating parameters include different voltages applied to read memory cells in the group.

5. The memory sub-system of claim 4 , wherein the statistical data includes counts of memory cells in the group having a predetermined state when the different voltages are applied on the group of memory cells.

6. The memory sub-system of claim 4 , wherein the statistical data includes count differences, each being a difference between:
a first count of memory cells in the group having a predetermined state when a first read voltage is applied on the group of memory cells; and
a second count of memory cells in the group having the predetermined state when a second read voltage is applied on the group of memory cells.

7. The memory sub-system of claim 1 , wherein the plurality of options include a first decoder and a second decoder that consumes more energy than the first decoder in operation.

8. The memory sub-system of claim 7 , wherein the second decoder uses both hard bit data determined from the group of memory cells at read voltages and soft bit data determined from the group of memory cells at voltages having predetermined offsets from the read voltages; and the first decoder uses the hard bit data without the soft bit data.

9. The memory sub-system of claim 8 , wherein the calibration circuit is configured to compute the read voltages for determination of the hard bit data based on the signal and noise characteristics.

10. The memory sub-system of claim 8 , wherein the data integrity classifier is implemented in the memory component; and the soft bit data is determined based on the prediction generated by the data integrity classifier.

11. The memory sub-system of claim 8 , wherein the data integrity classifier is implemented via the processing device; and the memory sub-system is configured to instruct the memory component to perform a read-retry when the prediction indicates a failure of decoders available in the memory sub-system in decoding the encoded data.

12. The memory sub-system of claim 8 , wherein the data integrity classifier is implemented via the processing device; and the memory sub-system is configured to instruct the memory component to provide the soft bit data when the prediction indicates the second decoder is to be used to decode the encoded data.

13. A method, comprising:
transmitting, by a processing device in a memory sub-system, a command to a memory component of the memory sub-system to retrieve encoded data from an address;
measuring, in response to the command and during execution of the command in the memory component, signal and noise characteristics of a group of memory cells formed on an integrated circuit die using a calibration circuit of the memory component enclosed in an integrated circuit package;
generating, by a data integrity classifier configured in the memory sub-system, a prediction based on the signal and noise characteristics, wherein the prediction is generated prior to the encoded data being decoded;
selecting, by the memory sub-system based on the prediction, an option from the plurality of options; and
decoding the encoded data using the selected option.

14. The method of claim 13 , wherein the signal and noise characteristics include statistics of memory cells in the group read at different levels of voltage.

15. The method of claim 14 , wherein the plurality of options include decoders taking different inputs, using different amounts of power in decoding, and having different latency in decoding.

16. The method of claim 15 , wherein the prediction is based on machine learning to identify the option.

17. A non-transitory computer storage medium storing instructions which, when executed by a computing system, cause the computing system to perform a method, the method comprising:
transmitting, by a processing device in a memory sub-system, a command to a memory component of the memory sub-system to retrieve encoded data from an address, wherein in response to the command and during execution of the command, a calibration circuit of the memory component measures signal and noise characteristics of a group of memory cells formed on an integrated circuit die;
receiving, from the memory component as a response to the command, the signal and noise characteristics;
generating, by a data integrity classifier configured in the memory sub-system, a prediction based on the signal and noise characteristics, wherein the prediction comprises a prediction that the encoded data will fail a test of data integrity; and
selecting, by the memory sub-system based on the prediction, an option from a plurality of options for processing of the encoded data retrieved from the group of memory cells.

18. The non-transitory computer storage medium of claim 17 , wherein the plurality of options include decoding the encoded data using different decoders and instructing the memory component to retry-read at the address without decoding the encoded data.

19. The non-transitory computer storage medium of claim 18 , wherein the prediction includes a confidence level of the prediction.

20. The non-transitory computer storage medium of claim 19 , wherein the decoding is performed using an error correction code, or a low-density parity-check code.

21. The non-transitory computer storage medium of claim 17 , wherein the prediction is made before the test of data integrity is actually performed on the encoded data.

22. The non-transitory computer storage medium of claim 17 , wherein the prediction is made prior to the encoded data being transferred to a decoder.

23. A non-transitory computer storage medium storing instructions which, when executed by a computing system, cause the computing system to perform a method, the method comprising:
transmitting, by a processing device in a memory sub-system, a first command to a memory component of the memory sub-system to retrieve first encoded

Assignees

• Micron Technology Inc

Inventors

• Khayat Patrick Robert
• Fitzpatrick James
• Alhussien Abdelhakim S
• Parthasarathy Sivagnanam

Classifications

• G06F11/1076 Primary

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

• G06N5/04

  Inference or reasoning models · CPC title

• G06N20/00

  Machine learning · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• H03M13/1102

  Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes · CPC title