Semiconductor packages

Patent metadata

Field	Value
Publication number	US-11735532-B2
Application number	US-202217664132-A
Country	US
Kind code	B2
Filing date	May 19, 2022
Priority date	Dec 26, 2019
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

A semiconductor package includes a lower connection structure, a semiconductor chip on the lower connection structure, an upper connection structure including a first conductive pattern layer on the semiconductor chip, a first insulating layer on the first conductive pattern layer, a second conductive pattern layer on the first insulating layer, a first via penetrating the first insulating layer to extend between the first conductive pattern layer and the second conductive pattern layer, and a second insulating layer extending between a side surface of the first via and the first insulating layer, and an intermediate connection structure between the lower connection structure and the upper connection structure. A chemical composition of the first insulating layer may differ from a chemical composition of the second insulating layer.

First claim

What is claimed is:

1. A semiconductor package comprising:
a semiconductor chip;
an intermediate connection structure comprising an intermediate insulating layer on sides of the semiconductor chip and an intermediate via penetrating the intermediate insulating layer;
a lower connection structure comprising a lower insulating layer on a lower surface of the semiconductor chip and on a lower surface of the intermediate connection structure and a lower conductive pattern layer on the lower insulating layer and connected to the semiconductor chip and the intermediate via;
an upper connection structure including a first upper conductive pattern layer on the semiconductor chip, a first upper insulating layer on the first upper conductive pattern layer, a second upper insulating layer on the first upper insulating layer, a second upper conductive pattern layer on the second upper insulating layer, a first upper via penetrating the first upper insulating layer and the second upper insulating layer to connect between the second upper conductive pattern layer and the first upper conductive pattern layer and a second upper via penetrating the first upper insulating layer and the second upper insulating layer to connect between the second upper conductive pattern layer and the intermediate via; and
an external connection terminal on a lower surface of the lower connection structure and connected to the lower conductive pattern layer,
wherein a portion of the first upper conductive pattern layer is configured to be grounded,
wherein a portion of the second upper conductive pattern layer is configured to transmit signals, and
wherein an entirety of the first conductive pattern layer is configured to be grounded.

2. The semiconductor package of claim 1 , further comprising a sealing layer between an upper surface of the semiconductor chip and the first upper conductive pattern layer.

3. The semiconductor package of claim 1 , wherein the second upper insulating layer further extends between the second upper conductive pattern layer and the first upper insulating layer.

4. The semiconductor package of claim 1 , wherein the portion of the first upper conductive pattern layer that is configured to be grounded is a first portion, and
wherein the first upper conductive pattern layer further comprises a second portion that is configured to transmit signals.

5. The semiconductor package of claim 1 , wherein the portion of the second upper conductive pattern layer that is configured to transmit signals is a first portion,
wherein the second upper conductive pattern layer further comprises a second portion that is configured to be grounded, and
wherein the portion of the first upper conductive pattern layer is configured to be grounded through the first via and the second portion of the second upper conductive pattern layer.

6. The semiconductor package of claim 1 , wherein the first upper conductive pattern layer is indirectly electrically connected to the intermediate connection structure by the second upper conductive pattern layer.

7. A semiconductor package comprising:
a semiconductor chip;
an intermediate connection structure comprising an intermediate insulating layer on sides of the semiconductor chip and an intermediate via penetrating the intermediate insulating layer;
a lower connection structure comprising a lower insulating layer on a lower surface of the semiconductor chip and on a lower surface of the intermediate connection structure and a lower conductive pattern layer on the lower insulating layer and connected to the semiconductor chip and the intermediate via;
an upper connection structure including a first upper conductive pattern layer on the semiconductor chip, a first upper insulating layer on the first upper conductive pattern layer, a second upper insulating layer on the first upper insulating layer, a second upper conductive pattern layer on the second upper insulating layer, a first upper via penetrating the first upper insulating layer and the second upper insulating layer to connect between the second upper conductive pattern layer and the first upper conductive pattern layer, wherein a chemical composition of the first upper insulating layer differs from a chemical composition of the second upper insulating layer; and
an external connection terminal on a lower surface of the lower connection structure and connected to the lower conductive pattern layer,
wherein the first upper insulating layer comprises a composite material including a matrix and a filler in the matrix, the filler including silica, and
wherein the second upper insulating layer does not comprise the filler.

8. The semiconductor package of claim 7 , further comprising a sealing layer between an upper surface of the semiconductor chip and the first upper conductive pattern layer.

9. The semiconductor package of claim 7 , wherein the upper connection structure further comprises a second upper via penetrating the first upper insulating layer and the second upper insulating layer to connect between the second upper conductive pattern layer and the intermediate via.

10. The semiconductor package of claim 7 , wherein the second upper insulating layer further extends between the second upper conductive pattern layer and the first upper insulating layer.

11. The semiconductor package of claim 7 , wherein a portion of the first upper conductive pattern layer is configured to be grounded, and
wherein a portion of the second upper conductive pattern layer is configured to transmit signals.

12. A semiconductor package comprising:
a semiconductor chip;
an intermediate connection structure comprising an intermediate insulating layer on sides of the semiconductor chip and an intermediate via penetrating the intermediate insulating layer;
a lower connection structure comprising a lower insulating layer on a lower surface of the semiconductor chip and on a lower surface of the intermediate connection structure and a lower conductive pattern layer on the lower insulating layer and connected to the semiconductor chip and the intermediate via;
an upper connection structure including a first upper conductive pattern layer on the semiconductor chip, a first upper insulating layer on the first upper conductive pattern layer, a second upper insulating layer on the first upper insulating layer, a second upper conductive pattern layer on the second upper insulating layer, a first upper via penetrating the first upper insulating layer and the second upper insulating layer to connect between the second upper conductive pattern layer and the first upper conductive pattern layer, wherein a thickness of the first upper conductive pattern layer is less than a thickness of the second upper conductive pattern layer; and
an external connection terminal on a lower surface of the lower connection structure and connected to the lower conductive pattern layer,
wherein the first upper insulating layer comprises a composite material including a matrix and a filler in the matrix, the filler including silica, and
wherein the second upper insulating layer does not comprise the filler.

13. The semiconductor package of claim 12 , further comprising a sealing layer between an upper surface of the semiconductor chip and the first upper conductive pattern layer.

14. The semiconductor package of claim 12 , wherein the upper connection structure further comprises a second upper via penetrating the first upper insulating layer and the second upper insulating layer to connect between the second upper conductive pattern layer and the intermediate via.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Joonsung
• Lee Doohwan
• Ko Taeho
• Kim Bongsoo
• Park Seokbong

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/851

  Dispositions of multiple connectors or interconnections · CPC title