Power delivery network for CFET with buried power rails

Patent metadata

Field	Value
Publication number	US-11735525-B2
Application number	US-201916659251-A
Country	US
Kind code	B2
Filing date	Oct 21, 2019
Priority date	Oct 21, 2019
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

A semiconductor device includes a first power rail, a first power input structure, a circuit and a first middle-of-line rail. The first power rail is formed in a first rail opening within a first isolation trench on a substrate. The first power input structure is configured to connect with a first terminal of a power source that is external of the semiconductor device to receive electrical power from the power source. The circuit is formed, on the substrate, by layers between the first power rail and the first power input structure. The first middle-of-line rail is formed by one or more of the layers that form the circuit. The first middle-of-line rail is configured to deliver the electrical power from the first power input structure to the first power rail, and the first power rail provides the electrical power to the circuit for operation.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first power rail;
a first power input structure configured to connect with a first terminal of a power source that is external of the semiconductor device to receive electrical power from the power source;
an active device formed between the first power rail and the first power input structure; and
a first middle-of-line rail that is formed by a plurality of layers, the first middle-of-line rail being configured to deliver the electrical power from the first power input structure to the first power rail, the first power rail providing the electrical power to the active device for operation, topmost and bottommost ones of the layers of the first middle-of-line rail being as high as and leveled with top and bottom surfaces of the active device, respectively.

2. The semiconductor device of claim 1 , further comprising:
a second power rail parallel with the first power rail;
a second power input structure configured to connect with a second terminal of the power source, and to receive, with the first power input structure, the electrical power from the power source; and
a second middle-of-line rail that is formed by a plurality of layers, the second middle-of-line rail being parallel with the first middle-of-line rail, and the first and second middle-of-line rails being configured to deliver the electrical power from the first and second input structures to the first and second power rails, the first and second power rails providing the electrical power to the active device for operation.

3. The semiconductor device of claim 1 , wherein:
the active device includes a cell row of cell circuits that have a same cell height; and
the first middle-of-line rail includes a section in a power tap cell that is disposed in the cell row, the power tap cell having the same cell height as the cell circuits.

4. The semiconductor device of claim 3 , wherein:
at least one of the layers of the first middle-of-line rail is used to form connections within a cell circuit.

5. The semiconductor device of claim 3 , wherein:
the active device includes multiple cell rows of cell circuits; and
the first middle-of-line rail is formed of sections respectively in power tap cells disposed in the multiple cell rows.

6. The semiconductor device of claim 5 , wherein
the power tap cells are aligned in a column, and the sections in the respective power tap cells are conductively connected to form the first middle-of-line rail.

7. The semiconductor device of claim 5 , wherein each section of the sections in the respective power tap cells is connected to the first power rail by at least a power via, and is connected to a metal rail by at least a contact.

8. The semiconductor device of claim 2 , wherein:
the first and second middle-of-line rails are perpendicular to the first and second power rails.

9. The semiconductor device of claim 1 , wherein:
the active device includes a second transistor and a first transistor that is disposed above the second transistor in a vertical direction that is parallel to a direction in that the active device is formed between the first power rail and the first power input structure.

10. The semiconductor device of claim 9 , wherein:
the first middle-of-line rail includes a first layer for forming a local interconnect in the first transistor, a second layer for forming a local interconnect in the second transistor, and a strap layer to merge the first layer and the second layer.

11. The semiconductor device of claim 1 , further comprising:
an upper metal layer power delivery network formed between the first power input structure and the first middle-of-line rail, the upper metal layer power delivery network configured to deliver the electric power from the first power input structure to the first middle-of-line rail.

12. The semiconductor device of claim 11 , further comprising:
first to seventh metal layers stacked over one another sequentially between the first power input structure and the first middle-of-line rail,
wherein the upper metal layer power delivery network includes metal wires that are formed in the first to seventh metal layers.

13. The semiconductor device of claim 10 , wherein the first layer is the topmost one of the layers, and the second layer is the bottommost one of the layers.

Assignees

• Tokyo Electron Ltd

Inventors

• Liebmann Lars
• Smith Jeffrey
• Devilliers Anton
• Chanemougame Daniel

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title