Method for forming semiconductor device structure with source/drain contact

Patent metadata

Field	Value
Publication number	US-11735470-B2
Application number	US-202017097409-A
Country	US
Kind code	B2
Filing date	Nov 13, 2020
Priority date	Nov 13, 2020
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

A semiconductor device structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes a source/drain structure formed beside the gate structure. The structure also includes a contact structure formed over the source/drain structure. The structure also includes a dielectric structure extending into the contact structure. The dielectric structure and the source/drain structure are separated by the contact structure.

First claim

What is claimed is:

1. A method for forming a semiconductor device structure, comprising:
forming a fin structure over a substrate;
forming a gate structure across the fin structure;
growing a source/drain structure next to the gate structure;
depositing an ILD structure over the fin structure;
forming a first opening in the ILD structure exposing the source/drain structure in a first region of the substrate;
conformally depositing a conductive layer over a sidewall and a bottom surface of the first opening;
filling a dielectric material in the first opening;
etching back the conductive layer to form a first recess surrounding a top portion of the dielectric material;
filling a cap layer in the first recess; and
planarizing the dielectric material to expose top surfaces of the conductive layer and the dielectric material in the first region.

2. The method for forming the semiconductor device structure as claimed in claim 1 , wherein after etching back the conductive layer, the top surface of the dielectric material is substantially level with a top surface of the ILD structure.

3. The method for forming the semiconductor device structure as claimed in claim 1 , further comprising:
conformally depositing a glue layer in the first opening before depositing the conductive layer; and
etching back the glue layer to expose a top surface of the glue layer from the first recess.

4. The method for forming the semiconductor device structure as claimed in claim 1 , further comprising:
forming a second opening in the ILD structure in a second region of the substrate;
filling the conductive layer over a sidewall and a bottom surface of the second opening; and
depositing the dielectric material over the conductive layer in the second opening,
wherein a bottom surface of the dielectric material is higher than a top surface of the gate structure in the second region.

5. The method for forming the semiconductor device structure as claimed in claim 4 , further comprising:
removing the dielectric material in the second region to expose the conductive layer in the second opening.

6. The method for forming the semiconductor device structure as claimed in claim 1 , further comprising:
forming a first liner layer over a sidewall of the gate structure; and
forming a second liner layer over the sidewall of the first opening,
wherein the first liner layer and the second liner layer are separated by the ILD structure in the first region.

7. A method for forming a semiconductor device structure, comprising:
forming a fin structure over a substrate;
forming a gate structure across the fin structure;
forming a source/drain structure beside the gate structure;
forming a contact structure over the source/drain structure;
forming a dielectric structure extending into the contact structure,
wherein the dielectric structure and the source/drain structure are separated by the contact structure; and
forming a first cap layer surrounding an upper portion of a sidewall of the dielectric structure.

8. The method for forming the semiconductor device structure as claimed in claim 7 , wherein a height of a middle portion of the contact structure is less than a height of a side portion of the contact structure.

9. The method for forming the semiconductor device structure as claimed in claim 8 , wherein a horizontal thickness of the side portion of the contact structure is substantially the same as a vertical thickness of the middle portion of the contact structure.

10. The method for forming the semiconductor device structure as claimed in claim 7 , further comprising:
forming a glue layer before forming the contact structure,
wherein a top surface of the glue layer is lower than a top surface of the dielectric structure.

11. The method for forming the semiconductor device structure as claimed in claim 7 , further comprising:
forming a liner layer before forming the contact structure; and
forming the first cap layer over the contact structure and the liner layer,
wherein a top surface of the liner layer is substantially level with a top surface of the dielectric structure.

12. The method for forming the semiconductor device structure as claimed in claim 11 , further comprising:
forming a second cap layer over the gate structure,
wherein the first cap layer and the second cap layer are made of different materials.

13. The method for forming the semiconductor device structure as claimed in claim 7 , further comprising:
forming an ILD structure after forming the gate structure and before forming the contact structure.

14. A method for forming a semiconductor device structure, comprising:
forming a fin structure over a substrate;
forming a source/drain structure over the fin structure;
forming a first contact structure over the source/drain structure in a first region of the substrate;
forming a dielectric structure extending into the first contact structure; and
forming a first cap layer over the first contact structure and the dielectric structure, so that the dielectric structure is embedded in the first cap layer and the first contact structure, and a top surface of the dielectric structure is higher than a bottom surface of the first cap layer.

15. The method for forming the semiconductor device structure as claimed in claim 14 , further comprising:
forming a second contact structure over a second source/drain structure in a second region of the substrate; and
forming a second cap layer over the second contact structure,
wherein the first contact structure is wider than the second contact structure.

16. The method for forming the semiconductor device structure as claimed in claim 15 , wherein a bottom surface area of the second cap layer is substantially equal to a top surface area of the second contact structure.

17. The method for forming the semiconductor device structure as claimed in claim 15 , wherein a height of a middle portion of the second contact structure is substantially the same as a height of a side portion of the second contact structure.

18. The method for forming the semiconductor device structure as claimed in claim 14 , wherein the dielectric structure comprises SiC, LaO, AlO, AlON, ZrO, HfO, SiN, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN, ZrSi, SiOCN, SiOC, SiCN, LaO, SiO, or a combination thereof.

19. The method for forming the semiconductor device structure as claimed in claim 14 , wherein the first contact structure has a U-shape in a cross-sectional view.

20. The method for forming the semiconductor device structure as claimed in claim 10 , wherein the top surface of the glue layer is substantially level with a top surface of the contact structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liao Chun-Hung
• Huang Lin-Yu
• Chang Chia-Hao
• Chao Huang-Lin

Classifications

• H10W20/034

  bottomless barrier, adhesion or liner layers · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title