Compound feature generation in classification of error rate of data retrieved from memory cells

Patent metadata

Field	Value
Publication number	US-11726719-B2
Application number	US-202217939812-A
Country	US
Kind code	B2
Filing date	Sep 7, 2022
Priority date	Mar 2, 2020
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

A memory sub-system configured to: measure a plurality of sets of signal and noise characteristics of a group of memory cells in a memory device; determine a plurality of optimized read voltages of the group of memory cells from the plurality of sets of signal and noise characteristics respectively; generate features from the plurality of sets of signal and noise characteristics, including at least one compound feature generated from the plurality of sets of signal and noise characteristics; generate, using the features, a classification of a bit error rate of data retrievable from the group of memory cells; and control an operation to read the group of memory cells based on the classification.

First claim

What is claimed is:

1. A device, comprising:
memory cells; and
a circuit, configured to:
measure signal and noise characteristics of the memory cells in a plurality of separate regions of voltage;
compute at least one feature based on the signal and noise characteristics of the memory cells; and
classify, based at least in part on the feature, a bit error rate of data retrievable from the memory cells.

2. The device of claim 1 , wherein each respective region in the plurality of separate regions of voltage includes a read voltage applied to the memory cells in determination of the data retrievable from the memory cells.

3. The device of claim 2 , configured to control an operation to read the memory cells based on a classification of the bit error rate determined based at least in part on the feature.

4. The device of claim 3 , configured to decide, based on the classification, whether to re-calibrate voltages to read the memory cells.

5. The device of claim 3 , further comprising:
a plurality of decoders, wherein the device is configured to select, based on the classification, a decoder from the plurality of decoders to decode the data retrieved from the memory cells using the read voltage in the respective region.

6. The device of claim 2 , further comprising:
an integrated circuit die containing the memory cells; and
an integrated circuit package configured to enclose the integrated circuit die.

7. The device of claim 6 , wherein each of the plurality of separate regions of voltage includes a candidate for the read voltage and a respective set of signal and noise characteristics of the memory cells measured based on the candidate; and the circuit is configured to compute the read voltage based on the respective set of signal and noise characteristics of the memory cells measured based on the candidate.

8. The device of claim 7 , wherein the feature is a first feature; and the circuit is configured to:
measure a further set of signal and noise characteristics of the memory cells based on a further candidate of a further read voltage in a further region of voltage that is separate from the plurality of separate regions;
compute the further read voltage based on the further set of signal and noise characteristics of the memory cells; and
compute a second feature based on the first feature and the further set of signal and noise characteristics of the memory cells;
wherein the circuit is configured to classify the bit error rate based at least on the first feature and the second feature.

9. The device of claim 8 , wherein the circuit is configured to compute the first feature in parallel with measuring the further set of signal and noise characteristics of the memory cells.

10. The device of claim 7 , wherein the circuit is configured to apply a plurality of test voltages, configured according to the candidate, to the memory cells; and for each respective test voltage among the plurality of test voltages, the circuit is configured to determine, for the respective set of signal and noise characteristics, a count of a subset of the memory cells having a predetermined state when applied the respective test voltage.

11. A method, comprising:
measuring, by a device having memory cells, signal and noise characteristics of the memory cells in a plurality of separate regions of voltage;
computing at least one feature based on the signal and noise characteristics of the memory cells; and
classifying, based at least in part on the feature, a bit error rate of data retrievable from the memory cells.

12. The method of claim 11 , wherein each respective region in the plurality of separate regions of voltage includes a read voltage applied to the memory cells in determination of the data retrievable from the memory cells.

13. The method of claim 12 , further comprising:
controlling, based on a classification of the bit error rate determined based at least in part on the feature, an operation to read the memory cells.

14. The method of claim 13 , wherein the controlling includes deciding, based on the classification, whether to re-calibrate voltages to read the memory cells.

15. The method of claim 13 , wherein the controlling includes selecting, based on the classification, a decoder from a plurality of decoders to decode the data retrieved from the memory cells using the read voltage in the respective region.

16. The method of claim 12 , wherein each of the plurality of separate regions of voltage includes a candidate for the read voltage and a respective set of signal and noise characteristics of the memory cells measured based on the candidate; and the method further comprises:
computing the read voltage based on the respective set of signal and noise characteristics of the memory cells measured based on the candidate.

17. The method of claim 16 , wherein the feature is a first feature; and the method further comprises:
measuring a further set of signal and noise characteristics of the memory cells based on a further candidate of a further read voltage in a further region of voltage that is separate from the plurality of separate regions;
computing the further read voltage based on the further set of signal and noise characteristics of the memory cells; and
computing a second feature based on the first feature and the further set of signal and noise characteristics of the memory cells;
wherein the classifying is based at least on the first feature and the second feature; and
wherein the first feature is computed in parallel with the measuring of the further set of signal and noise characteristics of the memory cells.

18. The method of claim 16 , wherein the respective set of signal and noise characteristics is measured via:
applying a plurality of test voltages, configured according to the candidate, to the memory cells; and
determining, for each respective test voltage among the plurality of test voltages and for the respective set of signal and noise characteristics, a count of a subset of the memory cells having a predetermined state when applied the respective test voltage.

19. A system, comprising:
a processing device configured to provide a command; and
a memory device having memory cells and configured to:
measure, in response to the command, signal and noise characteristics of the memory cells in a plurality of separate regions of voltage;
compute at least one feature based on the signal and noise characteristics of the memory cells; and
classify, based at least in part on the feature, a bit error rate of data retrievable from the memory cells.

20. The system of claim 19 , wherein the feature is a first feature; and the memory device is further configured to:
measure a further set of signal and noise characteristics of the memory cells based on a further candidate of a further read voltage in a further region of voltage that is separate from the plurality of separate regions;
compute the further read voltage based on the further set of signal and noise characteristics of the memory cells; and
compute a second feature based on the first feature and the further set of signal and noise characteristics of the memory cells;
wherein the memory device is configured to classify the bit error rate based at least on the first feature and the second feature; and
wherein the memory device is configured to compute the first feature in parallel with measuring the further set of signal and noise characteristics of the memory cells.

Assignees

• Micron Technology Inc

Inventors

• Parthasarathy Sivagnanam
• Fitzpatrick James
• Khayat Patrick Robert
• Alhussien Abdelhakim S

Classifications

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title