Determining a blended timing constraint that satisfies multiple timing constraints and user-selected specifications

Patent metadata

Field	Value
Publication number	US-11720732-B2
Application number	US-202117402739-A
Country	US
Kind code	B2
Filing date	Aug 16, 2021
Priority date	Aug 16, 2021
Publication date	Aug 8, 2023
Grant date	Aug 8, 2023

Abstract

Embodiments of the invention are directed to a computer-implemented method of determining timing constraints of a first component-under-design (CUD). The computer-implemented method includes accessing, using a processor, a plurality of timing constraint requirements configured to be placed on the first CUD by one or more second CUDs, wherein each of the plurality of timing constraint requirements is specifically designed for the CUD. The processor is used to perform a comparative analysis of each of the plurality of timing constraints to identify a single timing constraint that satisfies each of the plurality of timing constraints.

First claim

What is claimed is:

1. A computer-implemented method of analyzing timing-related design options of a first component-under-design (CUD), the computer-implemented method comprising:
accessing, using a processor, a plurality of timing constraint requirements placed on the first CUD by one or more second CUDs;
wherein each of the plurality of timing constraint requirements is specifically designed for the first CUD; and
performing, using the processor, a comparative analysis of each of the plurality of timing constraint requirements to identify a single timing constraint requirement that satisfies each of the plurality of timing constraint requirements.

2. The computer-implemented method of claim 1 , wherein:
the comparative analysis to identify the single timing constraint that satisfies each of the plurality of timing constraint requirements also comprises incorporating within the comparative analysis specification settings of the first CUD; and
the specification settings are determined by a designer of:
the first CUD;
the one or more second CUDs; or
the first CUD and the one or more second CUDs.

3. The computer-implemented method of claim 1 , wherein the comparative analysis comprises:
determining common attributes of the plurality of timing constraint requirements, wherein the common attributes comprise attributes that are present in each of the plurality of timing constraint requirements;
determining unique attributes among the plurality of timing constraint requirements, wherein the unique attributes comprise attributes that are present in some but not all of the plurality of timing constraint requirements;
determining maximum and minimum values of the common attributes; and
determining maximum and minimum values of the unique attributes.

4. The computer-implemented method of claim 1 , wherein:
the plurality of timing constraint requirements comprises a plurality of sets of timing constraint requirements;
each of the plurality of sets of timing constraint requirements is associated with a unique one of a plurality of pins of the first CUD; and
performing the comparative analysis comprises applying the comparative analysis to each one of the plurality of pins of the first CUD to identify the single timing constraint requirement for each of the plurality of sets of timing constraint requirements.

5. The computer-implemented method of claim 1 further comprising using the single timing constraint requirement to generate a timing constraint requirement rule.

6. The computer-implemented method of claim 5 further comprising providing the timing constraint requirement rule to a timing engine of a static timing analysis (STA) system.

7. The computer-implemented method of claim 6 further comprising using the timing engine to apply the timing constraint requirement rule to the first CUD.

8. A computer system for analyzing timing-related design options of a first component-under-design, the computer system comprising a memory communicatively coupled to a processor, wherein the processor is configured to perform processor operations comprising:
accessing a plurality of timing constraint requirements configured to be placed on the first CUD by one or more second CUDs;
wherein each of the plurality of timing constraint requirements is specifically designed for the first CUD; and
performing a comparative analysis of each of the plurality of timing constraint requirements to identify a single timing constraint requirement that satisfies each of the plurality of timing constraint requirements.

9. The computer system of claim 8 , wherein:
the comparative analysis to identify the single timing constraint requirement that satisfies each of the plurality of timing constraint requirements also comprises incorporating within the comparative analysis specification settings of the first CUD; and
the specification settings are determined by a designer of:
the first CUD;
the one or more second CUDs; or
the first CUD and the one or more second CUDs.

10. The computer system of claim 8 , wherein the comparative analysis comprises:
determining common attributes of the plurality of timing constraint requirements, wherein the common attributes comprise attributes that are present in each of the plurality of timing constraint requirements;
determining unique attributes among the plurality of timing constraint requirements, wherein the unique attributes comprise attributes that are present in some but not all of the plurality of timing constraint requirements;
determining maximum and minimum values of the common attributes; and
determining maximum and minimum values of the unique attributes.

11. The computer system of claim 8 , wherein:
the plurality of timing constraint requirements comprises a plurality of sets of timing constraint requirements;
each of the plurality of sets of timing constraint requirements is associated with a unique one of a plurality of pins of the first CUD; and
performing the comparative analysis comprises applying the comparative analysis to each one of the plurality of pins of the first CUD to identify the single timing constraint requirement for each of the plurality of sets of timing constraint requirements.

12. The computer system of claim 8 , wherein the processor operations further comprise using the single timing constraint requirement to generate a timing constraint requirement rule.

13. The computer system of claim 12 , wherein the processor operations further comprise providing the timing constraint requirement rule to a timing engine of a static timing analysis (STA) system.

14. The computer system of claim 13 , wherein the processor operations further comprise using the timing engine to apply the timing constraint requirement rule to the first CUD.

15. A computer program product for analyzing timing-related design options of a first component-under-design (CUD), the computer program product comprising a computer readable program stored on a computer readable storage medium, wherein the computer readable program, when executed on the processor, causes the processor to perform processor operations comprising:
accessing a plurality of timing constraint requirements configured to be placed on the first CUD by one or more second CUDs;
wherein each of the plurality of timing constraint requirements is specifically designed for the first CUD; and
performing a comparative analysis of each of the plurality of timing constraint requirements to identify a single timing constraint requirement that satisfies each of the plurality of timing constraint requirements.

16. The computer program product of claim 15 , wherein:
the comparative analysis to identify the single timing constraint requirement that satisfies each of the plurality of timing constraint requirements also comprises incorporating within the comparative analysis specification settings of the first CUD; and
the specification settings are determined by a designer of:
the first CUD;
the one or more second CUDs; or
the first CUD and the one or more second CUDs.

17. The computer program product of claim 15 , wherein the comparative analysis comprises:
determining common attributes of the plurality of timing constraint requirements, wherein the common attributes comprise attributes that are present in each of the plurality of timing constraint requirements;
determining unique attributes among the plurality of timing constraint requirements, wherein the unique attributes comprise attributes that are present in some but not all of the plurality of timing constraint r

Assignees

• IBM

Inventors

• Cavitt Chris Aaron
• Bruen Brandon Albert
• Foreman Eric
• Surprise Jesse Peter

Classifications

• G06F30/3315 Primary

  using static timing analysis [STA] · CPC title

• G06F30/347

  Physical level, e.g. placement or routing · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title