Circuit generation based on zero wire load assertions

Patent metadata

Field	Value
Publication number	US-10657211-B2
Application number	US-201815957959-A
Country	US
Kind code	B2
Filing date	Apr 20, 2018
Priority date	Apr 20, 2018
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

Zero wire load based assertions are generated. A zero wire load report is generated for a set of logic in a hardware description language corresponding to a circuit design. A set of assertions is identified for the circuit design by parsing the zero wire load report based in part on real data values corresponding to best case delays for one or more input pins and one or more output pins in a plurality of macros of the circuit design. A circuit may be fabricated based on the set of assertions.

First claim

What is claimed is:

1. A system for generating zero wire load based assertions comprising:
a processor configured to perform a method, the method comprising:
generating, via a zero wire load tool, a zero wire load report for a set of logic in a hardware description language corresponding to a circuit design;
identifying a set of zero-wire-load-based assertions for the circuit design by parsing the zero wire load report based in part on real data values corresponding to best case delays for one or more input pins and one or more output pins in a plurality of macros of the circuit design, the real data values being actual delay values according to a hardware description language simulation, and an assertion of the set of zero-wire-load-based assertions including a statement in the hardware description language that determines a Boolean condition; and
initiating fabrication of a circuit based on the set of zero-wire-load-based assertions.

2. The system of claim 1 , wherein the method further comprises parsing the zero wire load report based on unwritten logic.

3. The system of claim 1 , wherein the method further comprises identifying, based on at least one broken path existing, at least one broken path based on the set of zero-wire-load-based assertions, the at least one broken path being identified where an associated best case assertion of the set of zero-wire-load-based assertions is smaller than a circuit feedback assertion.

4. The system of claim 1 , wherein the set of zero-wire-load-based assertions comprises a delay and a slack for the one or more input pins or the one or more output pins in each macro of the plurality of macros.

5. The system of claim 1 , wherein the set of zero-wire-load-based assertions comprises an estimated time of arrival value indicating a delay for an output pin in the circuit design.

6. The system of claim 1 , wherein the set of zero-wire-load-based assertions comprise a pin in standard value indicating a combination of delay and slack for at least one input pin or at least one output pin in the circuit design.

7. The system of claim 1 , wherein the set of zero-wire-load-based assertions comprises a pin out standard value indicating a load for one or more of the output pins in the circuit design.

8. The system of claim 1 , wherein the zero wire load report comprises one of the following selected from the group consisting of: a standard gate delay, a fanout value, and a length of a device in the circuit design.

9. A method of generating zero wire load based assertions comprising:
generating, via a processor executing a zero wire load tool, a zero wire load report for a set of logic in a hardware description language corresponding to a circuit design;
identifying, via the processor, a set of zero-wire-load-based assertions for the circuit design by parsing the zero wire load report based in part on real data values corresponding to best case delays for one or more input pins and one or more output pins in a plurality of macros of the circuit design, the real data values being actual delay values according to a hardware description language simulation, and an assertion of the set of zero-wire-load-based assertions including a statement in the hardware description language that determines a Boolean condition; and
initiating fabrication of a circuit based on the set of zero-wire-load-based assertions.

10. The method of claim 9 , further comprising parsing the zero wire load report based on unwritten logic.

11. The method of claim 9 , further comprising identifying, based on at least one broken path existing, at least one broken path based on the set of zero-wire-load-based assertions, the at least one broken path being identified where an associated best case assertion of the set of zero-wire-load-based assertions is smaller than a circuit feedback assertion.

12. The method of claim 9 , wherein the set of zero-wire-load-based assertions comprise a delay and a slack for the one or more input pins or the one or more output pins in each macro of the plurality of macros.

13. The method of claim 9 , wherein the set of zero-wire-load-based assertions comprises an estimated time of arrival value indicating a delay for an output pin in the circuit design.

14. The method of claim 9 , wherein the set of zero-wire-load-based assertions comprises a pin in standard value indicating a combination of delay and slack for at least one input pin or at least one output pin in the circuit design.

15. The method of claim 9 , wherein the set of zero-wire-load-based assertions comprises a pin out standard value indicating a load for one or more of the output pins in the circuit design.

16. The method of claim 9 , wherein the zero wire load report comprises one of the following selected from the group consisting of: a standard gate delay, a fanout value, and a length of a device in the circuit design.

17. A computer program product for generating zero wire load based assertions, the computer program product comprising:
a computer readable storage medium readable by a processing circuit and storing instructions for performing a method comprising:
generating, via a zero wire load tool, a zero wire load report for a set of logic in a hardware description language corresponding to a circuit design;
identifying a set of zero-wire-load-based assertions for the circuit design by parsing the zero wire load report based in part on real data values corresponding to best case delays for one or more input pins and one or more output pins in a plurality of macros of the circuit design, the real data values being actual delay values according to a hardware description language simulation, and an assertion of the set of zero-wire-load-based assertions including a statement in the hardware description language that determines a Boolean condition; and
initiating fabrication of a circuit based on the set of zero-wire-load-based assertions.

18. The computer program product of claim 17 , wherein the method further comprises parsing the zero wire load report based on unwritten logic.

19. The computer program product of claim 17 , wherein the method further comprises identifying, based on at least one broken path existing, at least one broken path based on the set of zero-wire-load-based assertions, the at least one broken path being identified where an associated best case assertion of the set of zero-wire-load-based assertions is smaller than a circuit feedback assertion.

20. The computer program product of claim 17 , wherein the set of zero-wire-load-based assertions comprises a delay and a slack for the one or more input pins or the one or more output pins in each macro of the plurality of macros.

Assignees

• IBM

Inventors

• Plotkin Limor
• Raz Shiran
• Maroz Yaniv
• Geva Ofer

Classifications

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/30

  Circuit design · CPC title

• G06F2111/02

  CAD in a network environment, e.g. collaborative CAD or distributed simulation · CPC title

• G06F2111/20

  Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules · CPC title