Integrated circuit design with optimized timing constraint configuration

Patent metadata

Field	Value
Publication number	US-10831958-B2
Application number	US-201816143842-A
Country	US
Kind code	B2
Filing date	Sep 27, 2018
Priority date	Sep 27, 2018
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

Generating a design of an integrated circuit by analyzing a physical design of an integrated circuit by determining, for a pin of a circuit of the integrated circuit, that a candidate timing constraint for signal arrival time at the pin is later than a current timing constraint for signal arrival time at the pin, determining that a slack value associated with the current timing constraint has a greater negative value than a predefined negative slack threshold value, determining that the current timing constraint is within a user-defined range of signal arrival time values associated with the pin, determining that the candidate timing constraint is earlier than a latest-allowable signal arrival time at the pin, setting the current timing constraint equal to the candidate timing constraint, and generating a revised physical design of the integrated circuit that incorporates the current timing constraint.

First claim

What is claimed is:

1. A method for generating a design of an integrated circuit, the method comprising:
analyzing a physical design of an integrated circuit by evaluating a set of criteria comprising:
determining, for a pin of a circuit of the integrated circuit, that a candidate timing constraint for signal arrival time at the pin is later than a current timing constraint for signal arrival time at the pin,
determining that a slack value associated with the current timing constraint has a greater negative value than a predefined negative slack threshold value associated with the current timing constraint,
determining that the current timing constraint is within a user-defined range of signal arrival time values associated with the pin, and
determining that the candidate timing constraint is earlier than a latest-allowable signal arrival time at the pin;

based upon determining that the physical design does not meet each of the set of criteria, setting the candidate timing constraint to a new candidate timing constraint and repeating the analyzing,
based upon determining that the physical design meets each of the set of criteria:
setting the current timing constraint equal to the candidate timing constraint; and
generating a revised physical design of the integrated circuit that incorporates the current timing constraint.

2. The method according to claim 1 and further comprising performing multiple iterations of the analyzing, setting, and generating corresponding to multiple physical designs of the integrated circuit.

3. The method according to claim 2 wherein each of the iterations is performed after a timing analysis of the circuit is performed to determine an estimated signal arrival time at the pin and the slack value associated with the current timing constraint.

4. The method according to claim 3 wherein the iterations are performed until, for each pin of each circuit of the integrated circuit, the estimated signal arrival time at the pin meets the current timing constraint for signal arrival time at the pin within a specified tolerance.

5. The method according to claim 2 and further comprising determining the candidate timing constraint for a second of any two successive iterations of the multiple iterations by estimating a signal arrival time at the pin during a first of the two successive iterations.

6. The method according to claim 1 and further comprising performing the analyzing, setting, and generating for each of a plurality of circuits of the integrated circuit.

7. The method according to claim 6 and further comprising performing the analyzing, setting, and generating for each of a plurality of macros of the integrated circuit.

8. The method according to claim 1 and further comprising performing the analyzing, setting, and generating wherein the pin is an output pin of the circuit or an input pin of the circuit.

9. The method according to claim 1 and further comprising performing the analyzing, setting, and generating wherein the arrival time is of a signal rise or a signal fall.

10. A system for generating a design of an integrated circuit, the system comprising:
design automation apparatus configured to
analyze a physical design of an integrated circuit by evaluating a set of criteria comprising:
determining, for a pin of a circuit of an integrated circuit, that a candidate timing constraint for signal arrival time at the pin is later than a current timing constraint for signal arrival time at the pin,
determining that a slack value associated with the current timing constraint has a greater negative value than a predefined negative slack threshold value associated with the current timing constraint,
determining that the current timing constraint is within a user-defined range of signal arrival time values associated with the pin, and
determining that the candidate timing constraint is earlier than a latest-allowable signal arrival time at the pin,

based upon determining that the physical design does not meet each of the set of criteria, set the candidate timing constraint to a new candidate timing constraint and repeat the analyzing,
based upon determining that the physical design meets each of the set of criteria:
set the current timing constraint equal to the candidate timing constraint, and
generate a revised physical design of the integrated circuit that incorporates the current timing constraint.

11. The system according to claim 10 wherein the design automation apparatus is configured to analyze the physical design, set the current timing constraint, and generates the revised physical design in multiple iterations corresponding to multiple physical designs of the integrated circuit.

12. The system according to claim 11 wherein each of the iterations is performed after a timing analysis of the circuit is performed to determine an estimated signal arrival time at the pin and the slack value associated with the current timing constraint.

13. The system according to claim 12 wherein the iterations are performed until, for each pin of each circuit of the integrated circuit, the estimated signal arrival time at the pin meets the current timing constraint for signal arrival time at the pin within a specified tolerance.

14. The system according to claim 11 wherein the design automation apparatus is configured to determine the candidate timing constraint for a second of any two successive iterations of the multiple iterations by estimating a signal arrival time at the pin doting a first of the two successive iterations.

15. The system according to claim 10 wherein the design automation apparatus is configured to analyze the physical design, set the current timing constraint, and generates the revised physical design for each of a plurality of circuits of the integrated circuit.

16. The system according to claim 15 wherein the design automation apparatus is configured to analyze the physical design, set the current timing constraint, and generates the revised physical design for each of a plurality of macros of the integrated circuit.

17. The system according to claim 10 wherein the pin is an output pin of the circuit or an input pin of the circuit.

18. The system according to claim 10 wherein the arrival time is of a signal rise or a signal fall.

19. A computer program product for generating a design of an integrated circuit, the computer program product comprising:
a non-transitory, computer-readable storage medium; and
computer-readable program code embodied in the storage medium, wherein the computer-readable program code is configured to
analyze a physical design of an integrated circuit by evaluating a set of criteria comprising:
determining, for a pin of a circuit of the integrated circuit, that a candidate timing constraint for signal arrival time at the pin is later than a current timing constraint for signal arrival time at the pin,
determining that a slack value associated with the current timing constraint has a greater negative value than a predefined negative slack threshold value associated with the current timing constraint,
determining that the current timing constraint is within a user-defined range of signal arrival time values associated with the pin, and
determining that the candidate timing constraint is earlier than a latest-allowable signal arrival time at the pin;

based upon determining that the physical design does not meet each of the set of criteria, setting the candidate timing constraint to a new candidate timing constraint and repeating the analy

Assignees

• IBM

Inventors

• Geva Ofer
• Raz Shiran
• Maroz Yaniv

Classifications

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F30/337

  Design optimisation · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F2111/04

  Constraint-based CAD · CPC title