Selective boundary overlay insertion for hierarchical circuit design

Patent metadata

Field	Value
Publication number	US-9971861-B2
Application number	US-201615040086-A
Country	US
Kind code	B2
Filing date	Feb 10, 2016
Priority date	Feb 10, 2016
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

Aspects include techniques for selective boundary overlay insertion for hierarchical circuit design. A method may include determining, by a processing device, a block type of a child block. The method may further include electively inserting, by the processing device, at least one of an instantiated boundary overlay and a merged boundary overlay into the hierarchical circuit design based on the block type of the child block. The instantiated boundary overlay enables a parent block to pass a testing at an out-of-context level, and the merged boundary overlay enables the parent block to continue to pass the testing when the child block is inserted into the parent block associated with the child block.

First claim

What is claimed is:

1. A computer-implemented method for boundary overlay insertion for hierarchical circuit design, the method comprising:
determining, by a processing device, a block type of a child block, wherein the block type is one of a custom designed circuit block type and a gate level block type;
inserting, by the processing device, an instantiated boundary overlay into the hierarchical circuit design based on the block type of the child block being the custom designed circuit block type;
inserting, by the processing device, a merged boundary overlay into the hierarchical circuit design based on the block type of the child block being the gate level block type,
wherein the instantiated boundary overlay enables a parent block to pass a testing at an out-of-context level, and
wherein the merged boundary overlay enables the parent block to continue to pass the testing when the child block is inserted into the parent block associated with the child block; and
causing a circuit to be fabricated based at least in part on the hierarchical circuit design subsequent to passing the testing.

2. The computer-implemented method of claim 1 , wherein the instantiated boundary overlay remains with the parent block when the child block is inserted into the parent block associated with the child block.

3. The computer-implemented method of claim 1 , wherein the merged boundary overlay is removed from the parent block when the child block is inserted into the parent block associated with the child block.

4. The computer-implemented method of claim 1 , wherein the instantiated boundary overlay comprises a north/south boundary and an east/west boundary.

5. The computer-implemented method of claim 1 , wherein the merged boundary overlay comprises an east/west boundary.

6. A system for boundary overlay insertion for hierarchical circuit design, the system comprising:
a memory having computer readable instructions; and
a processor for executing the computer readable instructions, the computer readable instructions comprising:
determining a block type of a child block, wherein the block type is one of a custom designed circuit block type and a gate level block type;
inserting an instantiated boundary overlay into the hierarchical circuit design based on the block type of the child block being the custom designed circuit block type;
inserting a merged boundary overlay into the hierarchical circuit design based on the block type of the child block being the gate level block type,
wherein the instantiated boundary overlay enables a parent block to pass a testing at an out-of-context level, and
wherein the merged boundary overlay enables the parent block to continue to pass the testing when the child block is inserted into the parent block associated with the child block; and
causing a circuit to be fabricated based at least in part on the hierarchical circuit design subsequent to passing the testing.

7. The system of claim 6 , wherein the instantiated boundary overlay remains with the parent block when the child block is inserted into the parent block associated with the child block.

8. The system of claim 6 , wherein the merged boundary overlay is removed from the parent block when the child block is inserted into the parent block associated with the child block.

9. The system of claim 6 , wherein the instantiated boundary overlay comprises a north/south boundary and an east/west boundary.

10. The system of claim 6 , wherein the merged boundary overlay comprises an east/west boundary.

11. A computer program product for boundary overlay insertion for hierarchical circuit design, the computer program product comprising:
a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computer processor to cause the computer processor to:
determine a block type of a child block, wherein the block type is one of a custom designed circuit block type and a gate level block type;
insert an instantiated boundary overlay into the hierarchical circuit design based on the block type of the child block being the custom designed circuit block type;
insert a merged boundary overlay into the hierarchical circuit design based on the block type of the child block being the gate level block type,
wherein the instantiated boundary overlay enables a parent block to pass a testing at an out-of-context level, and
wherein the merged boundary overlay enables the parent block to continue to pass the testing when the child block is inserted into the parent block associated with the child block; and
cause a circuit to be fabricated based at least in part on the hierarchical circuit design subsequent to passing the testing.

12. The computer program product of claim 11 , wherein the instantiated boundary overlay remains with the parent block when the child block is inserted into the parent block associated with the child block.

13. The computer program product of claim 11 , wherein the merged boundary overlay is removed from the parent block when the child block is inserted into the parent block associated with the child block.

14. The computer program product of claim 11 , wherein the instantiated boundary overlay comprises a north/south boundary and an east/west boundary.

Assignees

• IBM

Inventors

• Behnen Erwin
• Gray Michael S
• Guzowski Matthew T
• Wolpert David S

Classifications

• G06F30/333

  Design for testability [DFT], e.g. scan chain or built-in self-test [BIST] · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F17/5081

  Physics · mapped topic