Generating parameters for statistical timing analysis of a circuit
US-2026057160-A1 · Feb 26, 2026 · US
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Foreman Eric patents
Foreman Eric is listed as an inventor on 22 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Foreman Eric |
| Total patents | 22 |
| First publication | Jul 31, 2018 |
| Latest publication | Feb 26, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Timing constraint auto-creation for integrated circuit testing
US-2025005244-A1 · Jan 2, 2025 · US
Timing analysis for non-scan latches
US-2024386175-A1 · Nov 21, 2024 · US
Timing analysis of a digital integrated circuit using intent based timing constraints
US-2024330551-A1 · Oct 3, 2024 · US
Determining a blended timing constraint that satisfies multiple timing constraints and user-selected specifications
US-11720732-B2 · Aug 8, 2023 · US
Determining a blended timing constraint that satisfies multiple timing constraints and user-selected specifications
US-2023047911-A1 · Feb 16, 2023 · US
Method of parameter creation
US-11074386-B2 · Jul 27, 2021 · US
Variable accuracy incremental timing analysis
US-10747925-B1 · Aug 18, 2020 · US
Variable accuracy incremental timing analysis
US-2020242205-A1 · Jul 30, 2020 · US
Superposition of canonical timing value representations in statistical static timing analysis
US-10691853-B2 · Jun 23, 2020 · US
Recent patents
Latest publications not already listed above.
Superposition of canonical timing value representations in statistical static timing analysis
US-2020134114-A1 · Apr 30, 2020 · US
Parameter collapsing and corner reduction in an integrated circuit
US-10546095-B2 · Jan 28, 2020 · US
Method of parameter creation
US-2019362046-A1 · Nov 28, 2019 · US
Method of parameter creation
US-10409938-B2 · Sep 10, 2019 · US
Method of parameter creation
US-2019243937-A1 · Aug 8, 2019 · US
Parameter collapsing and corner reduction in an integrated circuit
US-10354047-B2 · Jul 16, 2019 · US
Parameter collapsing and corner reduction in an integrated circuit
US-10296704-B2 · May 21, 2019 · US
Method of parameter creation
US-2018365360-A1 · Dec 20, 2018 · US
Parameter collapsing and corner reduction in an integrated circuit
US-2018357356-A1 · Dec 13, 2018 · US
Parameter collapsing and corner reduction in an integrated circuit
US-2018357355-A1 · Dec 13, 2018 · US
Parameter collapsing and corner reduction in an integrated circuit
US-2018357354-A1 · Dec 13, 2018 · US
Parameter collapsing and corner reduction in an integrated circuit
US-10037402-B1 · Jul 31, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 22 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F30/3312 | 14 |
| G06F2119/12 | 14 |
| G06F2111/08 | 12 |
| G06F30/3315 | 11 |
| G06F30/398 | 9 |