Three-dimensional memory devices having through stair contacts and methods for forming the same

Patent metadata

Field	Value
Publication number	US-11716846-B2
Application number	US-202017097635-A
Country	US
Kind code	B2
Filing date	Nov 13, 2020
Priority date	Jan 2, 2019
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

Embodiments of three-dimensional (3D) memory devices having through stair contacts (TSCs) and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack and a TSC. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. Edges of the interleaved conductive layers and dielectric layers define a staircase structure on a side of the memory stack. The TSC extends vertically through the staircase structure of the memory stack. The TSC includes a conductor layer and a spacer circumscribing the conductor layer.

First claim

What is claimed is:

1. A three-dimensional (3D) memory device, comprising:
a memory stack comprising a plurality of interleaved conductive layers and dielectric layers, wherein edges of the interleaved conductive layers and dielectric layers define a staircase structure on a side of the memory stack; and
a through stair contact (TSC) extending vertically through the staircase structure of the memory stack, wherein the TSC comprises a conductor layer and a spacer circumscribing the conductor layer, and the conductor layer of the TSC is isolated from all of the plurality of conductive layers of the memory stack by the spacer.

2. The 3D memory device of claim 1 , wherein the conductive layers of the memory stack comprise polysilicon, and the dielectric layers of the memory stack comprise silicon oxide.

3. The 3D memory device of claim 1 , wherein the conductor layer of the TSC comprises a metal.

4. The 3D memory device of claim 1 , wherein the spacer of the TSC has a uniform thickness.

5. The 3D memory device of claim 1 , further comprising a channel structure extending vertically through an inner region of the memory stack, wherein the staircase structure is disposed in an outer region of the memory stack.

6. The 3D memory device of claim 5 , wherein the TSC is disposed inside the outer region of the memory stack.

7. The 3D memory device of claim 5 , wherein the TSC extends vertically through a smaller number of the conductive layers and dielectric layers of the memory stack than the channel structure.

8. The 3D memory device of claim 1 , wherein a cross-section of the TSC has a circular shape.

9. The 3D memory device of claim 1 , further comprising a peripheral device above or below the memory stack.

10. The 3D memory device of claim 9 , further comprising a first substrate on which the memory stack is formed, and a second substrate on which the peripheral device is formed.

11. The 3D memory device of claim 10 , further comprising an interlayer dielectric (ILD) layer between the first substrate and the memory stack.

12. The 3D memory device of claim 10 , wherein the first substrate comprises silicon, and the TSC is in contact with the first substrate.

13. The 3D memory device of claim 1 , further comprising a peripheral contact outside of the memory stack, wherein the peripheral contact comprises a conductor layer and a spacer circumscribing the conductor layer.

14. The 3D memory device of claim 1 , further comprising a word line contact in contact with one of the conductive layers of the memory stack at the staircase structure.

15. The 3D memory device of claim 14 , wherein a cross-section of the word line contact and a cross-section of the TSC have a same shape.

16. A three-dimensional (3D) memory device, comprising:
a memory stack comprising a plurality of interleaved conductive layers and dielectric layers, wherein an edge of the memory stack comprises a staircase structure comprising a plurality of stairs, each stair comprises a landing area of a corresponding conductive layer that is uncovered by an adjacent conductive layer above the corresponding conductive layer; and
a through stair contact (TSC) extending vertically through a first landing area and a lower portion the staircase structure below the first landing area, wherein the TSC comprises a vertical conductor structure and a spacer laterally surrounding the vertical conductor structure, and the vertical conductor structure is isolated from a first conductive layer corresponding to the first landing area by the spacer.

17. The 3D memory device of claim 16 , further comprising:
a word line contact extending vertically and in contact with a second landing area without penetrating the staircase structure.

18. The 3D memory device of claim 17 , wherein:
the word line contact and the vertical conductor structure of the TSC comprise a same conductive material.

19. The 3D memory device of claim 17 , wherein:
a lateral dimension of the word line contact is less than a lateral dimension of the vertical conductor structure of the TSC.

20. The 3D memory device of claim 15 , wherein:
a lateral dimension of the word line contact is less than a lateral dimension of the TSC.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Wei Qinxiang
• Sun Jianhua
• Xia Ji

Classifications

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title