Matchless plasma source for semiconductor wafer fabrication

Patent metadata

Field	Value
Publication number	US-11716805-B2
Application number	US-202117558332-A
Country	US
Kind code	B2
Filing date	Dec 21, 2021
Priority date	Oct 18, 2017
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

A matchless plasma source is described. The matchless plasma source includes a controller that is coupled to a direct current (DC) voltage source of an agile DC rail to control a shape of an amplified square waveform that is generated at an output of a half-bridge transistor circuit. The matchless plasma source further includes the half-bridge transistor circuit used to generate the amplified square waveform to power an electrode, such as an antenna, of a plasma chamber. The matchless plasma source also includes a reactive circuit between the half-bridge transistor circuit and the electrode. The reactive circuit has a high-quality factor to negate a reactance of the electrode. There is no radio frequency (RF) match and an RF cable that couples the matchless plasma source to the electrode.

First claim

The invention claimed is:

1. A system comprising:
a direct current (DC) rail having an output;
an arbitrary waveform generator coupled to the DC rail, wherein the arbitrary waveform generator is configured to provide a plurality of voltage values to the DC rail,
wherein the plurality of voltage values are provided to shape an amplified square waveform generated at the output of the DC rail, wherein the amplified square waveform is shaped to provide a shaped waveform at the output of the DC rail;
a reactive circuit coupled to the DC rail, wherein the reactive circuit is configured to receive the shaped waveform and remove a plurality of harmonics from the shaped waveform to provide a sinusoidal radio frequency (RF) waveform to a plasma chamber.

2. The system of claim 1 , wherein the DC rail includes a DC voltage source, a first transistor, and a second transistor, wherein the DC voltage source is coupled to the first transistor and the first transistor is coupled to the second transistor.

3. The system of claim 2 , wherein the first transistor includes a first drain terminal and a first source terminal, wherein the second transistor includes a second drain terminal and a second source terminal, wherein the DC voltage source is coupled to the first drain terminal, wherein the first source terminal is coupled to the second drain terminal, and the second source terminal is coupled to a ground potential, wherein the output is located between the first source terminal and the second drain terminal.

4. The system of claim 3 , wherein the reactive circuit is a capacitor, wherein the capacitor is coupled to the output of the DC rail.

5. The system of claim 1 , wherein the plurality of voltage values are provided to shape an envelope of the amplified square waveform.

6. The system of claim 5 , wherein the envelope is shaped to achieve multiple parameter states of the amplified square waveform, wherein each of the parameter states provides a corresponding parameter level.

7. The system of claim 1 , wherein the reactive circuit is a capacitor, wherein the capacitor is coupled to the output of the DC rail.

8. A plasma system comprising:
a matchless plasma source including:
a direct current (DC) rail having an output;
an arbitrary waveform generator coupled to the DC rail, wherein the arbitrary waveform generator is configured to provide a plurality of voltage values to the DC rail, wherein the plurality of voltage values are provided to shape an amplified square waveform generated at the output of the DC rail, wherein the amplified square waveform is shaped to provide a shaped waveform at the output of the DC rail;

a reactive circuit coupled to the DC rail, wherein the reactive circuit is configured to receive the shaped waveform and remove a plurality of harmonics from the shaped waveform to provide a sinusoidal radio frequency (RF) waveform; and
a plasma chamber including an electrode, wherein the electrode is coupled to the matchless plasma source to receive the sinusoidal RF waveform.

9. The plasma system of claim 8 , wherein the DC rail includes a DC voltage source, a first transistor, and a second transistor, wherein the DC voltage source is coupled to the first transistor and the first transistor is coupled to the second transistor.

10. The plasma system of claim 9 , wherein the first transistor includes a first drain terminal and a first source terminal, wherein the second transistor includes a second drain terminal and a second source terminal, wherein the DC voltage source is coupled to the first drain terminal, wherein the first source terminal is coupled to the second drain terminal, and the second source terminal is coupled to a ground potential, wherein the output is located between the first source terminal and the second drain terminal.

11. The plasma system of claim 10 , wherein the reactive circuit is a capacitor, wherein the capacitor is coupled to the output of the DC rail.

12. The plasma system of claim 8 , wherein the plurality of voltage values are provided to shape an envelope of the amplified square waveform.

13. The plasma system of claim 12 , wherein the envelope is shaped to achieve multiple parameter states of the amplified square waveform, wherein each of the parameter states provides a corresponding parameter level.

14. The plasma system of claim 8 , wherein the reactive circuit is a capacitor, wherein the capacitor is coupled to the output of the DC rail.

15. A method comprising:
providing a plurality of voltage values from an arbitrary waveform generator to a direct current (DC) rail having an output;
shaping, by the plurality of voltage values, an amplified square waveform generated at the output of the DC rail to provide a shaped waveform at the output;
removing a plurality of harmonics from the shaped waveform to provide a sinusoidal radio frequency (RF) waveform to a plasma chamber.

16. The method of claim 15 , wherein the DC rail includes a DC voltage source, a first transistor, and a second transistor, wherein the DC voltage source is coupled to the first transistor and the first transistor is coupled to the second transistor.

17. The method of claim 16 , wherein the first transistor includes a first drain terminal and a first source terminal, wherein the second transistor includes a second drain terminal and a second source terminal, wherein the DC voltage source is coupled to the first drain terminal, wherein the first source terminal is coupled to the second drain terminal, and the second source terminal is coupled to a ground potential, wherein the output is located between the first source terminal and the second drain terminal.

18. The method of claim 17 , wherein said removing the plurality of harmonics is performed by a reactive circuit, wherein the reactive circuit is a capacitor coupled to the output of the DC rail.

19. The method of claim 15 , wherein said shaping the amplified square waveform includes shaping an envelope of the amplified square waveform.

20. The system of claim 19 , wherein said shaping the envelope of the amplified square waveform is performed to achieve multiple parameter states of the amplified square waveform, wherein each of the parameter states provides a corresponding parameter level.

Assignees

• Lam Res Corp

Inventors

• Long Maolin
• Wang Yuhou
• Marsh Ricky
• Paterson Alex

Classifications

• H05H2242/10

  Cooling arrangements · CPC title

• H03F3/2173

  of the bridge type · CPC title

• H05H2242/24

  Radiofrequency or microwave generators · CPC title

• H01J37/32183 Primary

  Matching circuits · CPC title

• H01J37/248

  Components associated with high voltage supply · CPC title