Semiconductor device having active fin pattern at cell boundary

Patent metadata

Field	Value
Publication number	US-11705456-B2
Application number	US-202117200179-A
Country	US
Kind code	B2
Filing date	Mar 12, 2021
Priority date	Aug 21, 2020
Publication date	Jul 18, 2023
Grant date	Jul 18, 2023

Abstract

A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first standard cell disposed on a substrate in a first row, the first standard cell having a first cell height;
a second standard cell disposed on the substrate in a second row adjacent to the first row, the second standard cell having a second cell height different from the first cell height; and
a power line extending in a first direction along a boundary between the first standard cell and the second standard cell,
wherein the first standard cell comprises:
a first base active region defined by a device isolation layer; and
a plurality of first fin patterns disposed on the first base active region and extending in the first direction,

wherein the second standard cell comprises:
a second base active region defined by the device isolation layer; and
a plurality of second fin patterns disposed on the second base active region and extending in the first direction,

wherein the device isolation layer is disposed between the first base active region and the second base active region,
wherein a central line of the power line and a central line of the device isolation layer are offset in a second direction, perpendicular to the first direction, the central line of the power line and the central line of the device isolation layer extending in the first direction,
wherein the plurality of first fin patterns comprises a first external fin pattern overlapping the power line in a vertical direction, and
wherein the first external fin pattern is disposed at the boundary between the first standard cell and the second standard cell.

2. The semiconductor device of claim 1 , wherein the first standard cell further comprises:
a first gate structure intersecting the first external fin pattern and extending in the second direction;
a plurality of first source/drain regions disposed on the first external fin pattern on both sides of the first gate structure;
a first contact structure disposed below the power line, the first contact structure extending in the first direction and connected to the plurality of first source/drain regions; and
a conductive via connecting the first contact structure to the power line,
wherein the first external fin pattern is electrically connected to the power line.

3. The semiconductor device of claim 1 , wherein no dummy pattern is disposed at an entire boundary of the first standard cell.

4. The semiconductor device of claim 1 , wherein the plurality of first fin patterns comprises a plurality of first internal fin patterns arranged at a first interval, and
wherein a first internal fin pattern among the plurality of first internal fin patterns is disposed adjacent to the first external fin pattern at a second interval different from the first interval.

5. The semiconductor device of claim 1 , wherein the first standard cell further comprises a plurality of first channel layers disposed vertically on the plurality of first fin patterns and spaced apart from each other,
wherein the second standard cell further comprises a plurality of second channel layers disposed vertically on the plurality of second fin patterns and spaced apart from each other, and
wherein a width of each first channel layer of the plurality of first channel layers in the second direction is different from a width of each second channel layer of the plurality of second channel layers in the second direction.

6. A semiconductor device comprising:
a first standard cell disposed on a substrate in a first row, the first standard cell having a first cell height;
a second standard cell disposed on the substrate in a second row adjacent to the first row, the second standard cell having a second cell height different from the first cell height; and
a power line extending in a first direction along a boundary between the first standard cell and the second standard cell,
wherein the first standard cell comprises:
a first base active region defined by a device isolation layer; and
a plurality of first fin patterns disposed on the first base active region and extending in the first direction,

wherein the second standard cell comprises:
a second base active region defined by the device isolation layer; and
a plurality of second fin patterns disposed on the second base active region and extending in the first direction,

wherein the device isolation layer is disposed between the first base active region and the second base active region,
wherein a central line of the power line and a central line of the device isolation layer are offset in a second direction, perpendicular to the first direction, the central line of the power line and the central line of the device isolation layer extending in the first direction,
wherein the first standard cell further comprises at least one first gate structure intersecting the plurality of first fin patterns and extending in the second direction, and
wherein the at least one first gate structure extends from the first standard cell to pass through the boundary between the first standard cell and the second standard cell.

7. The semiconductor device of claim 6 , wherein the at least one first gate structure comprises a plurality of first gate structures,
wherein a first gate structure of the plurality of first gate structures extends into the second standard cell, and
wherein other first gate structures of the plurality of first gate structures are spaced apart from each other in the first standard cell.

8. The semiconductor device of claim 6 , wherein the second standard cell further comprises a second gate structure intersecting the plurality of second fin patterns and extending in the second direction,
wherein the semiconductor device further comprises a gate separation pattern disposed between the at least one first gate structure and the second gate structure, and
wherein a central line of the gate separation pattern is offset from the central line of the power line in the second direction.

9. A semiconductor device comprising:
a substrate having a base active region;
a plurality of standard cells, each standard cell of the plurality of standard cells comprising:
a plurality of fin patterns disposed on the base active region of the substrate and extending in a first direction;
a gate structure intersecting the plurality of fin patterns and extending in a second direction intersecting the first direction; and
a plurality of source/drain regions disposed on both sides of the gate structure and on the plurality of fin patterns; and

a plurality of power lines, each power line of the plurality of power lines extending in the first direction along boundaries between adjacent standard cells of the plurality of standard cells and supplying power to the plurality of standard cells,
wherein the plurality of standard cells comprises a first standard cell and a second standard cell,
wherein the first standard cell comprises a first PMOS transistor region and a first NMOS transistor region, the first PMOS transistor region having a height in the second direction different from a height of the first NMOS transistor region,
wherein the second standard cell comprises a second PMOS transistor region and a second NMOS transistor region, the second PMOS transistor region having a height in the second direction different from a height of the second NMOS transistor region,
wherein a first cell height of the first standard cell in the second direction is substantially equal to a sum of the height of the first PMOS transistor region and the height of the first NMOS transistor region,
wherein a second cell height of the second standard cell in the second direction is substantially equal to a sum of the height of the second

Assignees

• Samsung Electronics Co Ltd

Inventors

• Baek Sanghoon
• Do Jungho
• Seo Jaewoo
• YU Jisu

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D84/853

  comprising FinFETs · CPC title