Semiconductor devices including an isolation insulating pattern with a first bottom surface, a second bottom surface, and a third bottom surface therebetween, where the third bottom surface has a different height than the first and second bottom surfaces

Patent metadata

Field	Value
Publication number	US-11705451-B2
Application number	US-202117394991-A
Country	US
Kind code	B2
Filing date	Aug 5, 2021
Priority date	Dec 17, 2020
Publication date	Jul 18, 2023
Grant date	Jul 18, 2023

Abstract

A semiconductor device includes a substrate including a boundary region between first and second regions, first active patterns on the first region, second active patterns on the second region, and an isolation insulating pattern on the boundary region between the first and second active patterns. A width of at least some of the first active patterns have different widths. Widths of the second active patterns may be equal to each other. A bottom surface of the isolation insulating pattern includes a first bottom surface adjacent to a corresponding first active pattern, a second bottom surface adjacent to a corresponding second active pattern, and a third bottom surface between the first bottom surface and the second bottom surface. The third bottom surface is located at a different height from those of the first and second bottom surfaces with respect to a bottom surface of the substrate.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate including a first region, a second region, and a boundary region between the first region and the second region;
first active patterns on the first region of the substrate;
second active patterns on the second region of the substrate; and
an isolation insulating pattern on the boundary region of the substrate, the isolation insulating pattern between the first active patterns and the second active patterns, wherein
a width of at least one of the first active patterns is different from a width of an other of the first active patterns, and widths of the second active patterns are equal to each other,
the isolation insulating pattern is between a corresponding first active pattern of the first active patterns and a corresponding second active pattern of the second active patterns,
a bottom surface of the isolation insulating pattern includes a first bottom surface adjacent to the corresponding first active pattern, a second bottom surface adjacent to the corresponding second active pattern, and a third bottom surface between the first bottom surface and the second bottom surface,
the third bottom surface is located at a different height from a height of the first bottom surface and a height of the second bottom surface with respect to a bottom surface of the substrate.

2. The semiconductor device of claim 1 , wherein
a first sidewall of the isolation insulating pattern is in contact with the corresponding first active pattern,
a second sidewall of the isolation insulating pattern is in contact with the corresponding second active pattern,
the bottom surface of the isolation insulating pattern is in contact with the substrate between the first sidewall and the second sidewall.

3. The semiconductor device of claim 1 , wherein the first active patterns and the second active patterns are spaced apart from each other in a first direction parallel to the bottom surface of the substrate and extend long in a second direction which is parallel to the bottom surface of the substrate and intersects the first direction,
wherein the widths of the first and second active patterns are widths in the first direction.

4. The semiconductor device of claim 3 , wherein the widths of the second active patterns are less than widths of at least some of the first active patterns.

5. The semiconductor device of claim 3 , further comprising:
first device isolation patterns between the first active patterns; and
second device isolation patterns between the second active patterns,
wherein each of the first device isolation patterns has a first width in the first direction, each of the second device isolation patterns has a second width in the first direction, and the isolation insulating pattern has a third width in the first direction,
wherein the third width is greater than the first width and the second width.

6. The semiconductor device of claim 3 , wherein the isolation insulating pattern extends long in the second direction between the corresponding first active pattern and the corresponding second active pattern, and
wherein the first bottom surface, the second bottom surface, and third bottom surface of the isolation insulating pattern extend long in the second direction.

7. The semiconductor device of claim 1 , wherein the third bottom surface is located at a lower height than the first bottom surface and the second bottom surface with respect to the bottom surface of the substrate.

8. The semiconductor device of claim 7 , further comprising:
first device isolation patterns between the first active patterns,
wherein the third bottom surface of the isolation insulating pattern is located at a lower height than bottom surfaces of the first device isolation patterns with respect to the bottom surface of the substrate.

9. The semiconductor device of claim 8 , further comprising:
second device isolation patterns between the second active patterns,
wherein the third bottom surface of the isolation insulating pattern is located at a lower height than bottom surfaces of the second device isolation patterns with respect to the bottom surface of the substrate.

10. The semiconductor device of claim 1 , wherein the third bottom surface is located at a higher height than the first bottom surface and the second bottom surface with respect to the bottom surface of the substrate.

11. The semiconductor device of claim 10 , further comprising:
first device isolation patterns between the first active patterns,
wherein the third bottom surface of the isolation insulating pattern is located at a higher height than bottom surfaces of the first device isolation patterns with respect to the bottom surface of the substrate.

12. The semiconductor device of claim 11 , further comprising:
second device isolation patterns between the second active patterns,
wherein the third bottom surface of the isolation insulating pattern is located at a higher height than bottom surfaces of the second device isolation patterns with respect to the bottom surface of the substrate.

13. The semiconductor device of claim 1 , further comprising:
first channel patterns on the first active patterns, respectively,
wherein each of the first channel patterns includes a plurality of first semiconductor patterns vertically spaced apart from each other on each of the first active patterns.

14. The semiconductor device of claim 13 , further comprising:
second channel patterns on the second active patterns, respectively,
wherein each of the second channel patterns includes a plurality of second semiconductor patterns vertically spaced apart from each other on each of the second active patterns.

15. The semiconductor device of claim 13 , further comprising:
second channel patterns on the second active patterns, respectively,
wherein each of the second channel patterns vertically protrudes from each of the second active patterns.

16. A semiconductor device comprising:
a substrate including a first region, a second region, and a boundary region between the first region and the second region;
first active patterns on the first region of the substrate and spaced apart from each other in a first direction parallel to a bottom surface of the substrate;
second active patterns on the second region of the substrate and spaced apart from each other in the first direction;
an isolation insulating pattern on the boundary region of the substrate, the isolation insulating pattern between the first active patterns and the second active patterns;
a first gate structure intersecting the first active patterns; and
a second gate structure intersecting the second active patterns, wherein
each of the first active patterns and the second active patterns has a width in the first direction, at least some of the first active patterns have different widths, and the second active patterns have equal widths,
the first gate structure extends on the at least some of the first active patterns having the different widths,
the isolation insulating pattern is between a corresponding first active pattern of the first active patterns and a corresponding second active pattern of the second active patterns, and
a bottom surface of the isolation insulating pattern includes a first bottom surface adjacent to the corresponding first active pattern, a second bottom surface adjacent to the corresponding second active pattern, and a recess surface recessed from the first bottom surface and second bottom surfaces into the substrate.

17. The semiconductor device of clai

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Inwon
• KIM Bosoon
• Park Jongsoon

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title