Merging lithography processes for gate patterning

US9691868B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9691868-B2
Application numberUS-201414283168-A
CountryUS
Kind codeB2
Filing dateMay 20, 2014
Priority dateNov 22, 2013
Publication dateJun 27, 2017
Grant dateJun 27, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Methods for fabricating devices on a die, and devices on a die. A method may include patterning a first region to create a first gate having a first gate length and a first contacted polysilicon pitch (CPP) with a first process. The first CPP is smaller than a single pattern lithographic limit. The method also includes patterning the first region to create a second gate having a second gate length or a second CPP with a second process. The second CPP is smaller than the single pattern lithographic limit. The second gate length is different than the first gate length.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for fabricating a plurality of devices on a die, comprising: patterning a first region to create a plurality of first gates having a first gate length and a contacted polysilicon pitch (CPP) with a first process, the CPP being smaller than a single pattern lithographic limit; patterning the first region according to a cell swap process; and then fabricating a pair of second gates arranged in place of some of the plurality of first gates, the second pair of gates having a second gate length and the CPP, the cell swap process being different from the first process, and the second gate length being different than the first gate length. 2. The method of claim 1 , in which the first process is a self-aligned double patterning (SADP) process. 3. The method of claim 2 , in which the second process is a litho-etch-litho-etch (LELE) process. 4. The method of claim 1 , in which the cell swap process is a second lithography process performed in between gates formed by the first process. 5. The method of claim 1 , in which the plurality of devices are integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit. 6. An apparatus, comprising: a plurality of first gate length devices having a first gate length and a contacted polysilicon pitch (CPP) in a first region, the CPP being smaller than a single pattern lithographic limit; and a pair of second gate length devices arranged in place of some of the plurality of first gate length devices in the first region, the pair of second gate length devices having a second gate length and the CPP, the second gate length being different than the first gate length. 7. The apparatus of claim 6 , in which the plurality of first gate length devices have a more uniform critical dimension uniformity than the pair of second gate length devices. 8. The apparatus of claim 6 , further comprising a third gate length device having a third gate length. 9. The apparatus of claim 6 integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit. 10. A method for fabricating a plurality of devices on a die, comprising: the step of patterning a first region to create a plurality of first gates having a first gate length and a contacted polysilicon pitch (CPP) with a first process, the CPP being smaller than a single pattern lithographic limit; the step of patterning the first region according to a cell swap process; and then fabricating a pair of second gates arranged in place of some of the plurality of first gates, the second pair of gates having a second gate length and the CPP, the cell swap process being different from the first process, and the second gate length being different than the first gate length. 11. The method of claim 10 , in which the plurality of devices are integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

Assignees

Inventors

Classifications

  • Aspects related to lithography, isolation or planarisation of the conductor · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

  • Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature (stitching G03F7/70475) · CPC title

  • Electricity · mapped topic

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9691868B2 cover?
Methods for fabricating devices on a die, and devices on a die. A method may include patterning a first region to create a first gate having a first gate length and a first contacted polysilicon pitch (CPP) with a first process. The first CPP is smaller than a single pattern lithographic limit. The method also includes patterning the first region to create a second gate having a second gate len…
Who is the assignee on this patent?
Qualcomm Inc
What technology area does this patent fall under?
Primary CPC classification G03F7/70466. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 27 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).