Method of fabricating semiconductor device

Patent metadata

Field	Value
Publication number	US-10096479-B2
Application number	US-201615395479-A
Country	US
Kind code	B2
Filing date	Dec 30, 2016
Priority date	Jul 16, 2014
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

Provided is a method of fabricating a semiconductor device. In the method, a double patterning technology is used to form various patterns with different widths.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
sequentially forming a lower layer and an upper layer on a substrate;
forming, on the upper layer, a first set of sacrificial patterns at a first region of the substrate and a second set of sacrificial patterns at a second region of the substrate;
forming first spacers on sidewalls of the first set of sacrificial patterns and second spacers on sidewalls of the second set of sacrificial patterns;
selectively removing the first set of sacrificial patterns and the second set of sacrificial patterns;
etching the upper layer exposed by the first and second spacers to form a first set of upper patterns and a second set of upper patterns under the respective first spacers and second spacers;
removing the first spacers and second spacers to expose top surfaces of the first and second sets of upper patterns;
forming third spacers on sidewalls of the second set of upper patterns, wherein each pattern of the first set of upper patterns has a first width, and each pattern of the second set of upper patterns and its corresponding third spacers has a second width greater than the first width; and
etching the lower layer to form a first set of lower patterns at the first region and a second set of lower patterns at the second region,
wherein each pattern of the first set of lower patterns has the first width, and each pattern of the second set of lower patterns has the second width.

2. The method of claim 1 , further comprising, after forming the third spacers on sidewalls of the second set of upper patterns, and before etching the lower layer to form a first set of lower patterns at the first region and a second set of lower patterns at the second region:
etching a buffer layer disposed between the upper patterns and the lower layer; and
using the etched buffer layer as a mask to etch the lower layer and form the first and second set of lower patterns.

3. The method of claim 2 ,
wherein the etched buffer layer includes a first set of buffer patterns formed under the first set of upper patterns using the first set of upper patterns as an etch mask, and the etched buffer layer includes a second set of buffer patterns formed under the second set of upper patterns and the third spacers using the second set of upper patterns and the third spacers as an etch mask,
wherein each buffer pattern of the second set of buffer patterns is formed to have the second width, and each buffer pattern of the first set of buffer patterns is formed to have the first width.

4. The method of claim 1 , further comprising:
forming a set of first fins on the substrate, each first fin corresponding to a lower pattern of the first set of lower patterns, and each first fin having the first width; and
forming a set of second fins on the substrate, each second fin corresponding to a lower pattern of the second set of lower patterns, and each second fin having the second width.

5. The method of claim 4 , wherein each fin of the first set of fins and the second set of fins is part of a transistor and includes a gate electrode formed thereon.

6. A method of fabricating a semiconductor device, comprising:
sequentially forming a lower layer and an upper layer on a substrate;
forming, on the upper layer, a first set of sacrificial patterns at a first region of the substrate and a second set of sacrificial patterns at a second region of the substrate;
forming first spacers on opposite sidewalls of each sacrificial pattern of the first set of sacrificial patterns and second spacers on opposite sidewalls of each sacrificial pattern of the second set of sacrificial patterns;
selectively removing the first set of sacrificial patterns and the second set of sacrificial patterns without removing the first or second spacers, thereby exposing part of the upper layer;
etching the upper layer exposed by the first and second spacers to form a first set of upper patterns and a second set of upper patterns under the respective first spacers and second spacers;
removing the first spacers and second spacers to expose top surfaces of the first and second sets of upper patterns;
forming third spacers on opposite sidewalls of each upper pattern of the first set of upper patterns, wherein each pattern of the first set of upper patterns has a first width, and each pattern of the second set of upper patterns and its corresponding third spacers has a second width greater than the first width; and
etching the lower layer using the first set of upper patterns, and the second set of upper patterns and corresponding third spacers to form first fins of the first region on the substrate, the first fins having the first width, and to form second fins of the second region on the substrate, the second fins having the second width.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoo Seunghan

Classifications

• H10P50/695 Primary

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H10P50/00 Primary

  Etching of wafers, substrates or parts of devices · CPC title

• H01L21/306 Primary

  Electricity · mapped topic

• H01L21/3085

  Electricity · mapped topic