Semiconductor devices including active patterns having different pitches and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-9755049-B2
Application number	US-201615000425-A
Country	US
Kind code	B2
Filing date	Jan 19, 2016
Priority date	Jan 21, 2015
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

Methods for fabricating semiconductor devices are provided including sequentially stacking hardmask layers, a first sacrificial layer, and a second sacrificial layer on a substrate, forming first mandrels on the first sacrificial layer by etching the second sacrificial layer, forming first spacers on side walls of the first mandrels, forming a photoresist pattern disposed outside a region from which the first mandrels have been removed, forming second and third mandrels by etching the first sacrificial layer using the first spacers and the photoresist pattern as respective etching masks, forming second and third spacers on side walls of the second and third mandrels, forming first and second active patterns respectively having first and second pitches by etching the hardmask layer and at least a portion of the substrate, and forming a device isolation layer so that upper portions of the first and second active patterns protrude therefrom.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
sequentially stacking hardmask layers, a first sacrificial layer, and a second sacrificial layer on a substrate;
etching the second sacrificial layer to form first mandrels on the first sacrificial layer;
forming first spacers on side walls of the first mandrels;
forming a photoresist pattern disposed outside a region from which the first mandrels have been removed, spaced apart from the first spacers, and having a line width greater than a line width of the first spacers;
etching the first sacrificial layer using the first spacers and the photoresist pattern as respective etching masks to form second mandrels and a third mandrel, respectively;
forming second spacers on side walls of the second mandrels and third spacers on side walls of the third mandrel;
forming first active patterns having a first pitch and second active patterns having a second pitch greater than the first pitch, by etching the hardmask layer and at least a portion of the substrate using the second and third spacers as respective etching masks; and
forming a device isolation layer so that upper portions of the first active patterns and the second active patterns protrude therefrom.

2. The method of claim 1 , wherein the first pitch ranges from 30 nm to 35 nm, and the second pitch ranges from 40 nm to 50 nm.

3. The method of claim 1 , wherein forming the second and third spacers is followed by removing the second mandrels and the third mandrel such that the second spacers and the third spacers having different pitches are retained in linear form.

4. The method of claim 1 :
wherein pitches of the second spacers are determined by a line width of the first spacer; and
wherein pitches of the third spacers are determined by a line width of the photoresist pattern.

5. The method of claim 1 , wherein the pitches of the third spacers are greater than the pitches of the second spacers.

6. The method of claim 1 , wherein the forming of the first spacers on side walls of the first mandrels comprises:
forming a first spacer material layer conformally covering the first mandrels; and etching back the first spacer material layer.

7. The method of claim 1 , wherein the forming of the second spacers and the third spacers on side walls of the second mandrels and the third mandrel comprises:
forming a second spacer material layer conformally covering the second mandrels and the third mandrel; and
etching back the second spacer material layer.

8. The method of claim 1 , wherein the first sacrificial layer and the second sacrificial layer comprises one of polycrystalline silicon, amorphous silicon, and spin on hardmask (SOH).

9. The method of claim 1 , wherein the hardmask layers comprises at least one of polycrystalline silicon, silicon oxide, and silicon nitride.

10. A method of fabricating a semiconductor device, comprising:
sequentially stacking hardmask layers, a first sacrificial layer, and a second sacrificial layer on a substrate;
etching the second sacrificial layer using a first photoresist pattern fanned on the second sacrificial layer as an etching mask to form first mandrels;
forming first spacers on side walls of the first mandrels;
forming a second photoresist pattern in a region from which the first mandrels have been removed, spaced apart from the first spacers, and having a line width greater than a line width of the first spacers;
etching the first sacrificial layer using the first spacers and the second photoresist pattern as respective etching masks to form second mandrels and a third mandrel, respectively, having different line widths;
forming second spacers on side walls of the second mandrels and third spacers on side walls of the third mandrel;
etching the hardmask layers using the second spacers and the third spacers having different pitches as an etching mask to form a hardmask pattern;
etching the substrate using the hardmask pattern as an etching mask to form first active patterns having a first pitch and second active patterns having a second pitch greater than the first pitch; and
forming a device isolation layer so that upper portions of the first active patterns and the second active patterns protrude therefrom.

11. The method of claim 10 , wherein the first pitch ranges from 30 nm to 35 nm, and the second pitch ranges from 40 nm to 50 nm.

12. The method of claim 10 , wherein distances between the second photoresist pattern and the first spacers adjacent to the second photoresist are substantially the same.

13. The method of claim 10 , wherein a line width of the third mandrel is greater than a line width of the second mandrel.

14. The method of claim 10 , wherein forming the second spacers and the third spacers is followed by removing the second mandrels and the third mandrel such that the second spacers and the third spacers having different pitches are retained in linear form.

15. The method of claim 10 :
wherein pitches of the second spacers are determined by a line width of the first spacers; and
wherein pitches of the third spacers are determined by a line width of the second photoresist pattern.

16. The method of claim 10 , wherein pitches of the third spacers are greater than pitches of the second spacers.

17. A method of manufacturing a semiconductor device, comprising:
sequentially stacking hardmask layers, a first sacrificial layer, and a second sacrificial layer on a substrate having a first region and a second region;
forming a first photoresist pattern on the second sacrificial layer in the first region;
etching the second sacrificial layer using the first photoresist pattern as an etching mask to form first mandrels on the first sacrificial layer in the first region;
forming first spacers on side walls of the first mandrels in the first region;
forming a second photoresist pattern on the first sacrificial layer in the first region, to be spaced apart from the first spacers and disposed outside a region from which the first mandrels have been removed, and forming a third photoresist pattern and a forth photoresist pattern having different line widths on the first sacrificial layer in the second region;
etching the first sacrificial layer using the first spacer and the second photoresist pattern as respective etching masks to form a second mandrel and a third mandrel, respectively, in the first region;
etching the first sacrificial layer using the third photoresist pattern and the fourth photoresist pattern as respective etching masks to form a forth mandrel and a fifth mandrel, respectively, in the second region;
forming second to fifth spacers on side walls of the second to fifth mandrels;
forming first active patterns having a first pitch in the first region, second active patterns having a second pitch greater than the first pitch in the first region, third active patterns having a third pitch in the second region, and fourth active patterns having a fourth pitch greater than the third pitch in the second region, by etching the hardmask layer and at least a portion of the substrate using the second to fifth spacers as respective etching masks; and
forming a device isolation layer so that upper portions of the first to fourth active patterns protrude therefrom,
wherein a line width of each of the second to fourth photoresist patterns is greater than a line width of the first spacer, and a line width of the fourth photoresist pattern is greater than a line width of each of the second and third photoresist patterns.

18. The method of

Assignees

• Samsung Electronics Co Ltd

Inventors

• Paak Sunhom Steve
• Kim Sung Min

Classifications

• H10P50/695 Primary

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10W10/0145

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10P76/40

  of masks comprising inorganic materials · CPC title

• H10P76/20 Primary

  of masks comprising organic materials · CPC title