Methods of micro-via formation for advanced packaging

Patent metadata

Field	Value
Publication number	US-11705365-B2
Application number	US-202117323381-A
Country	US
Kind code	B2
Filing date	May 18, 2021
Priority date	May 18, 2021
Publication date	Jul 18, 2023
Grant date	Jul 18, 2023

Abstract

The present disclosure relates to micro-via structures for interconnects in advanced wafer level semiconductor packaging. The methods described herein enable the formation of high-quality, low-aspect-ratio micro-via structures with improved uniformity, thus facilitating thin and small-form-factor semiconductor devices having high I/O density with improved bandwidth and power.

First claim

The invention claimed is:

1. A method of forming a micro-via structure in a semiconductor device, comprising:
laminating a polymeric material layer over a conductive layer on the semiconductor device, wherein the semiconductor device comprises:
a substrate;
an insulating layer atop the substrate; and
the conductive layer atop the insulating layer;
depositing a metal mask layer over the polymeric material layer;
applying, patterning, and developing a resist layer over the metal mask layer, wherein developing the resist layer forms a trench in the resist layer corresponding to a desired lateral dimension of the micro-via structure;
etching the metal mask layer through the trench in the developed resist layer, wherein etching the metal mask layer extends the trench into the metal mask layer and exposes a portion of the polymeric material layer; and
laser ablating the exposed portion of the polymeric material layer using an ultraviolet (UV) laser in a pulse-burst mode and the pulse burst mode provides pulses at frequency of 50 MHz or more and an energy between 5 nJ and 10 nJ, wherein laser ablating the exposed portion of the polymeric material layer forms the micro-via structure therein having the desired lateral dimension and exposes the conductive layer.

2. The method of claim 1 , wherein the polymeric material layer comprises an epoxy resin material having a ceramic filler.

3. The method of claim 1 wherein the metal mask layer comprises chromium (Cr).

4. The method of claim 1 , wherein the resist layer is a photoresist and is patterned via selective exposure to UV radiation.

5. The method of claim 1 , wherein the resist layer is patterned using direct write digital lithography.

6. The method of claim 1 , wherein the metal mask layer is dry-etched using an oxygen-based plasma.

7. The method of claim 1 , wherein the polymeric material layer is laser ablated using the UV laser with a wavelength between 345 nm and 355 nm.

8. A method of forming a micro-via structure in a semiconductor device, comprising:
laminating a polymeric material layer over a conductive layer of the semiconductor device, wherein the semiconductor device comprises:
a substrate;
an insulating layer atop the substrate; and
the conductive layer atop the insulating layer;
depositing a metal mask layer over the polymeric material layer;
applying, patterning, and developing a resist layer over the metal mask layer, wherein developing the resist layer forms a trench in the resist layer corresponding to a desired lateral dimension of the micro-via structure;
selectively etching the metal mask layer through the trench in the developed resist layer, wherein selectively etching the metal mask layer extends the trench into the metal mask layer and exposes a portion of the polymeric material layer;
laser ablating the exposed portion of the polymeric material layer using an ultraviolet (UV) laser in a pulse-burst mode and the pulse burst mode provides pulses at a frequency of 50 MHz or more and an energy between 5 nJ and 10 nJ, wherein laser ablating the exposed portion of the polymeric material layer forms the micro-via structure therein having the desired lateral dimension and exposes the conductive layer;
exposing the micro-via structure to a cleaning process to remove debris therefrom; and
selectively removing the metal mask layer from the polymeric material layer.

9. The method of claim 8 , wherein the metal mask layer comprises chromium (Cr).

10. The method of claim 8 , wherein the resist layer is patterned using direct write digital lithography.

11. The method of claim 8 , wherein the metal mask layer is selectively dry-etched using an oxygen-based plasma.

12. The method of claim 8 , wherein the micro-via structure has a lateral dimension between about 2 μm and about 10 μm.

13. The method of claim 8 , wherein the micro-via structure has a first lateral dimension between about 2 μm and about 15 μm, and a second later dimension between about 1 μm and about 8.5 μm.

14. A method of forming a micro-via structure in a semiconductor device, comprising:
laminating a polymeric material layer over a conductive layer of the semiconductor device, wherein the semiconductor device comprises:
a substrate;
an insulating layer atop the substrate; and
the conductive layer atop the insulating layer;

depositing a chromium mask layer over the polymeric material layer;
applying, patterning, and developing a resist layer over the chromium mask layer, wherein developing the resist layer forms a trench in the resist layer corresponding to a desired lateral dimension of the micro-via structure;
selectively etching the chromium mask layer through the trench in the developed resist layer, wherein selectively etching the chromium mask layer extends the trench into the chromium mask layer and exposes a portion of the polymeric material layer;
laser ablating the exposed portion of the polymeric material layer using an ultraviolet (UV) laser in a pulse-burst mode and wherein the pulse burst mode provides pulses at frequency of 50 MHz or more and an energy between 5 nJ and 10 nJ, wherein laser ablating the exposed portion of the polymeric material layer forms the micro-via structure therein having the desired lateral dimension, and wherein the conductive layer of the semiconductor device is utilized as a laser stop;
removing the resist layer from the chromium mask layer;
exposing the micro-via structure to a cleaning process to remove debris therefrom, wherein the cleaning process includes a dry fluorine-based plasma etch and a methanol-based wet clean; and
selectively removing the chromium mask layer from the polymeric material layer with a wet etch process.

Assignees

• Applied Materials Inc

Inventors

• Lei Wei-Sheng
• Leschkies Kurtis
• Gouk Roman
• Park Giback
• Cho Kyuil
• Chakraborty Tapash
• Chen Han-Wen
• Verhaverbeke Steven

Classifications

• H10W70/095

  of vias therein · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W70/681

  comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W90/00

  Package configurations · CPC title