Bridge interconnection with layered interconnect structures

Patent metadata

Field	Value
Publication number	US-11694960-B2
Application number	US-202117410716-A
Country	US
Kind code	B2
Filing date	Aug 24, 2021
Priority date	May 28, 2013
Publication date	Jul 4, 2023
Grant date	Jul 4, 2023

Abstract

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. An IC assembly, comprising:
a package substrate, the package substrate comprising a dielectric material;
a bridge in the package substrate, the bridge comprising silicon, wherein the dielectric material of the package substrate is over and in contact with the bridge;
a first joint over and electrically coupled to the bridge, the first joint in the dielectric material and extending above the dielectric material, and the first joint comprising copper;
a first layer on the first joint, the first layer comprising nickel;
a second joint over and electrically coupled to the bridge, the second joint in the dielectric material and extending above the dielectric material, and the second joint comprising copper;
a second layer on the second joint, the second layer comprising nickel;
a first interconnect structure in the package substrate, the first interconnect structure laterally spaced from a first side of the bridge, and the first interconnect in the dielectric material;
a second interconnect structure in the package substrate, the second interconnect structure laterally spaced from a second side of the bridge, and the second interconnect in the dielectric material;
a first die electrically coupled to the first joint and the first interconnect structure; and
a second die electrically coupled to the second joint and the second interconnect structure.

2. The IC assembly of claim 1 , wherein the first die is a processor, and the second die is part of a memory.

3. The IC assembly of claim 1 , wherein the first die is an ASIC, and the second die is part of a memory.

4. The IC assembly of claim 1 , wherein the first die is partially over the bridge and partially over the package substrate.

5. The IC assembly of claim 4 , wherein the second die is partially over the bridge and partially over the package substrate.

6. An IC assembly, comprising:
a package substrate, the package substrate comprising a dielectric material;
a bridge embedded in the package substrate, the bridge comprising silicon, wherein the dielectric material of the package substrate is over and in contact with the bridge;
a first joint over and electrically coupled to the bridge, the first joint in the dielectric material and extending above the dielectric material, and the first joint comprising copper;
a first layer on the first joint, the first layer comprising nickel;
a second joint over and electrically coupled to the bridge, the second joint in the dielectric material and extending above the dielectric material, and the second joint comprising copper;
a second layer on the second joint, the second layer comprising nickel;
a first interconnect structure in the package substrate, the first interconnect structure laterally spaced from a first side of the bridge, and the first interconnect in the dielectric material;
a second interconnect structure in the package substrate, the second interconnect structure laterally spaced from a second side of the bridge, and the second interconnect in the dielectric material;
a first die electrically coupled to the first joint and the first interconnect structure; and
a second die electrically coupled to the second joint and the second interconnect structure.

7. The IC assembly of claim 6 , wherein the first die is a processor, and the second die is part of a memory.

8. The IC assembly of claim 6 , wherein the first die is an ASIC, and the second die is part of a memory.

9. The IC assembly of claim 6 , wherein the first die is partially over the bridge and partially over the package substrate.

10. The IC assembly of claim 9 , wherein the second die is partially over the bridge and partially over the package substrate.

11. An IC assembly, comprising:
a package substrate, the package substrate comprising a dielectric material;
a bridge in the package substrate, the bridge comprising glass, wherein the dielectric material of the package substrate is over and in contact with the bridge;
a first joint over and electrically coupled to the bridge, the first joint in the dielectric material and extending above the dielectric material, and the first joint comprising copper;
a first layer on the first joint, the first layer comprising nickel;
a second joint over and electrically coupled to the bridge, the second joint in the dielectric material and extending above the dielectric material, and the second joint comprising copper;
a second layer on the second joint, the second layer comprising nickel;
a first interconnect structure in the package substrate, the first interconnect structure laterally spaced from a first side of the bridge, and the first interconnect in the dielectric material;
a second interconnect structure in the package substrate, the second interconnect structure laterally spaced from a second side of the bridge, and the second interconnect in the dielectric material;
a first die electrically coupled to the first joint and the first interconnect structure; and
a second die electrically coupled to the second joint and the second interconnect structure.

12. The IC assembly of claim 11 , wherein the first die is a processor, and the second die is part of a memory.

13. The IC assembly of claim 11 , wherein the first die is an ASIC, and the second die is part of a memory.

14. The IC assembly of claim 11 , wherein the first die is partially over the bridge and partially over the package substrate.

15. The IC assembly of claim 14 , wherein the second die is partially over the bridge and partially over the package substrate.

16. An IC assembly, comprising:
a package substrate, the package substrate comprising a dielectric material;
a bridge embedded in the package substrate, the bridge comprising glass, wherein the dielectric material of the package substrate is over and in contact with the bridge;
a first joint over and electrically coupled to the bridge, the first joint in the dielectric material and extending above the dielectric material, and the first joint comprising copper;
a first layer on the first joint, the first layer comprising nickel;
a second joint over and electrically coupled to the bridge, the second joint in the dielectric material and extending above the dielectric material, and the second joint comprising copper;
a second layer on the second joint, the second layer comprising nickel;
a first interconnect structure in the package substrate, the first interconnect structure laterally spaced from a first side of the bridge, and the first interconnect in the dielectric material;
a second interconnect structure in the package substrate, the second interconnect structure laterally spaced from a second side of the bridge, and the second interconnect in the dielectric material;
a first die electrically coupled to the first joint and the first interconnect structure; and
a second die electrically coupled to the second joint and the second interconnect structure.

17. The IC assembly of claim 16 , wherein the first die is a processor, and the second die is part of a memory.

18. The IC assembly of claim 16 , wherein the first die is an ASIC, and the second die is part of a memory.

19. The IC assembly of claim 16 , wherein the first die is partially over the bridge and partially over the package substrate.

20. The IC assembly of claim 19 , wherein the second die is partially over the bridge and partially over the package substrate.

Assignees

• Intel Corp

Inventors

• Liu Yueli
• Zhang Qinglei
• Schuckman Amanda E
• Zhang Rui

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/07236

  Soldering or alloying · CPC title