Bridge interconnection with layered interconnect structures

Patent metadata

Field	Value
Publication number	US-9640485-B2
Application number	US-201514836906-A
Country	US
Kind code	B2
Filing date	Aug 26, 2015
Priority date	May 28, 2013
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. An apparatus comprising:
a substrate;
an adhesive-mounted bridge adhesively-mounted and embedded in the substrate, the bridge being configured to route electrical signals between a first die and a second die; and
an interconnect structure electrically coupled with the bridge, the interconnect structure including:
a via structure including a first conductive material, the via structure being disposed to route the electrical signals through at least a portion of the substrate,
a barrier layer including a second conductive material disposed on the via structure, and
a solderable material including a third conductive material disposed on the barrier layer, wherein the first conductive material, the second conductive material and the third conductive material have different chemical compositions.

2. The apparatus of claim 1 , wherein:
the bridge includes a pad; and
the first conductive material is in direct contact with the pad.

3. The apparatus of claim 1 , wherein the via structure protrudes beyond a surface of an outermost build-up layer of the substrate.

4. The apparatus of claim 1 , wherein the barrier layer covers a surface of the via structure to inhibit diffusion of the first conductive material.

5. The apparatus of claim 1 , wherein the first die includes a processor and the second die includes a memory die or another processor.

6. The apparatus of claim 1 , wherein the electrical signals are input/output (I/O) signals.

7. The apparatus of claim 1 , wherein the substrate is a first substrate and the bridge includes a bridge substrate that comprises a semiconductor material including silicon (Si), and wherein the first substrate comprises an epoxy-based dielectric material.

8. The apparatus of claim 1 , wherein the bridge is embedded in the substrate using Ajinomoto Build-up Film (ABF) lamination.

9. The apparatus of claim 1 , wherein first conductive material comprises copper (Cu), the second conductive material comprises nickel (Ni), and the third conductive material comprises tin (Sn).

10. A system comprising:
a first die and a second die; and
a substrate with an adhesive-mounted bridge and an interconnect structure, the bridge adhesively-mounted and embedded in the substrate, the bridge and the interconnect structure being configured to route electrical signals between the first die and the second die, the interconnect structure electrically coupled with the bridge, the interconnect structure including:
a via structure including a first conductive material, the via structure being disposed to route the electrical signals through at least a portion of the substrate,
a barrier layer including a second conductive material disposed on the via structure, and
a solderable material including a third conductive material disposed on the barrier layer, wherein the first conductive material, the second conductive material and the third conductive material have different chemical compositions.

11. The system of claim 10 , wherein the substrate is a first substrate and the bridge includes a bridge substrate that comprises a semiconductor material, the semiconductor material including silicon (Si).

12. The system of claim 10 , wherein the barrier layer covers a surface of the via structure to inhibit diffusion of the first conductive material.

13. The system of claim 10 , wherein the first die includes a processor and the second die includes a memory die or another processor.

14. The system of claim 10 , wherein first conductive material comprises copper (Cu), the second conductive material comprises nickel (Ni), and the third conductive material comprises tin (Sn).

15. The system of claim 10 , further comprising:
a circuit board, wherein the substrate is electrically coupled with the circuit board and the circuit board is configured to route the electrical signals of the first die or the second die; and
one or more of an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera coupled with the circuit board.

16. The system of claim 10 , wherein the system is one of a wearable computer, a smartphone, a tablet, a personal digital assistant, a mobile phone, an ultra mobile PC, an ultrabook, a netbook, a notebook, a laptop, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.

Assignees

• Intel Corp

Inventors

• Liu Yueli
• Zhang Qinglei
• Schuckman Amanda E
• Zhang Rui

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/07236

  Soldering or alloying · CPC title