Embedded vialess bridges

Patent metadata

Field	Value
Publication number	US-9852994-B2
Application number	US-201615354061-A
Country	US
Kind code	B2
Filing date	Nov 17, 2016
Priority date	Dec 14, 2015
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

Embedded vialess bridges are provided. In an implementation, discrete pieces containing numerous conduction lines or wires in a 3-dimensional bridge piece are embedded where needed in a main substrate to provide dense arrays of signal, power, and electrical ground wires below the surface of the main substrate. Vertical conductive risers to reach the surface plane of the main substrate are also included in the discrete piece, for connecting to dies on the surface of the substrate and thereby interconnecting the dies to each other through the dense array of wires in the discrete piece. The discrete piece to be embedded may have parallel planes of conductors at regular intervals within itself, and thus may present a working surface homogeneously covered with the ends of vertical conductors available to connect surface components to each other and to ground and power at many places along the embedded piece.

First claim

The invention claimed is:

1. An apparatus, comprising: a first substrate for microelectronic devices; a second substrate of a nonconductive material bearing electrical conductors, the second substrate embedded in the first substrate to provide an embedded second substrate and embedded electrical conductors under a surface plane of the first substrate; vertical conductors in the embedded second substrate to interconnect the microelectronic devices on a surface of the first substrate with each other through the embedded electrical conductors, wherein the embedded second substrate is embedded in a superficial outer layer of the first substrate and comprises parallel layers, each layer made of individual electrical conduits, each layer of conduits interleaved with a layer of nonconductive insulator material to form a laminate block, the laminate block diced and embedded in the superficial outer layer at 90 degrees to a dicing plane to provide vialess vertical conductors.

2. The apparatus of claim 1 , wherein the embedded electrical conductors comprise a high concentration of wires or a dense array of conductors capable of replacing very fine high density traces on a surface of the first substrate.

3. The apparatus of claim 1 , wherein the embedded second substrate is embedded with parallel embedded conductors at 90 degrees with respect to the surface plane of the first substrate to provide the vertical conductors accessible at the surface plane of the first substrate.

4. The apparatus of claim 1 , wherein the embedded second substrate provides a high density signal conduction layer under a surface of the first substrate, the high density signal conduction layer accessible from the surface of the first substrate through the vertical conductors.

5. The apparatus of claim 4 , wherein the high density signal conduction layer comprises wide conduction traces or wires providing more reliable operation, higher signal fidelity, higher current, higher voltage, and higher power carrying capacity than traces and wire routing on a surface of the first substrate.

6. The apparatus of claim 1 , wherein the embedded second substrate provides at least one vertical plane of parallel power conductors or ground conductors under a horizontal surface plane of the first substrate.

7. The apparatus of claim 1 , wherein the embedded substrate is deeply embedded or formed in a core of the first substrate, or as part of the core of the first substrate.

8. The apparatus of claim 1 , wherein the second substrate of the nonconductive material is selected from the group consisting of a dielectric material, an insulator, an insulation material, a printed-circuit-board (PCB) material, a glass, an epoxy, a composite, a FR-4, plastic, a polymer, glass-reinforced epoxy laminate sheets, woven fiberglass cloth with epoxy resin binder, and a laminated block of insulation layers interleaving layers of individual vertical conductors.

9. A method, comprising: embedding a second substrate of a nonconductive material including a dense array of conductors, in a first substrate for microelectronic devices; interconnecting the microelectronic devices by attaching the microelectronic devices to vertical conductors of the embedded second substrate, the vertical conductors in communication with the dense array of conductors in the embedded second substrate; arranging parallel layers, each layer made of individual electrical conduits; interleaving each layer of conduits with a layer of a nonconductive insulator material to form a laminate block; dicing the laminate block at a dicing plane to make the second substrate including the dense array of conductors; and embedding the second substrate superficially in an outer layer of the first substrate at 90 degrees to the dicing plane to provide vialess vertical conductors.

10. The method of claim 9 , further comprising embedding the second substrate inside a core of the first substrate or as part of the core of the first substrate during manufacture.

11. The method of claim 9 , further comprising applying an adhesive to bond the embedded second substrate including the dense array of conductors to the first substrate.

12. The method of claim 9 , further comprising embedding the second substrate in the first substrate to form a protrusion of the second substrate above a surface plane of the first substrate; and lapping or polishing the second substrate and the first substrate to a flatness of the first substrate, wherein the vertical conductors remain accessible at variable depths of the lapping or the polishing.

13. The method of claim 9 , further comprising integrating wide wires in the second substrate to comprise the dense array of conductors; embedding the second substrate in the first substrate to provide replacement of a very fine line aspect of surface traces of the first substrate; and selecting the wide wires to provide more reliable operation, higher signal fidelity, higher current, higher voltage, and higher power carrying capacity than the surface traces of the first substrate.

14. The method of claim 9 , further comprising integrating numerous wide wires at various depths of the second substrate to provide the dense array of conductors.

15. The method of claim 9 , further comprising attaching conductive pads or balls to the vertical conductors for connecting a die to the vertical conductors.

16. The method of claim 9 , further comprising embedding the second substrate including the dense array of conductors in the first substrate to interconnect a top surface and a bottom surface of the first substrate.

17. The method of claim 9 , further comprising embedding multiple instances of the second substrate at different depths in the same first substrate to provide signal, power, and ground layers beneath a surface plane of the first substrate.

18. The method of claim 9 , wherein the second substrate of the nonconductive material is selected from the group consisting of a dielectric material, an insulator, an insulation material, a printed-circuit-board (PCB) material, a glass, an epoxy, a composite, a FR-4, plastic, a polymer, glass-reinforced epoxy laminate sheets, woven fiberglass cloth with epoxy resin binder, and a laminated block of insulation layers interleaving layers of individual vertical conductors.

Assignees

• Invensas Corp

Inventors

• Haba Belgacem

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W72/072

  of bump connectors · CPC title