Layout design for threshold voltage tuning

Patent metadata

Field	Value
Publication number	US-11694958-B2
Application number	US-202016891600-A
Country	US
Kind code	B2
Filing date	Jun 3, 2020
Priority date	Jun 3, 2020
Publication date	Jul 4, 2023
Grant date	Jul 4, 2023

Abstract

Semiconductor device layout designs for Vt tuning are provided. In one aspect, a semiconductor device is provided. The semiconductor device includes: at least one first metal line in contact with a source or drain of an FET; at least one second metal line in contact with a gate of the FET, wherein the first metal line crosses the second metal line; and an oxygen diffusion blocking layer on top of the at least one first metal line in an overlap area of the at least one first metal line and the at least one second metal line. A method of forming a semiconductor device is also provided.

First claim

What is claimed is:

1. A semiconductor device, comprising:
at least one first metal line in contact with a source or drain of a field-effect transistor (FET);
at least one second metal line in contact with a gate of the FET, wherein the first metal line crosses the second metal line; and
an oxygen diffusion blocking layer on top of the at least one first metal line in only an overlap area of the at least one first metal line and the at least one second metal line.

2. The semiconductor device of claim 1 , further comprising:
a vertical interconnect (V0) present over the at least one first metal line.

3. The semiconductor device of claim 2 , wherein the V0 is present over the at least one first metal line and the oxygen diffusion blocking layer in the overlap area.

4. The semiconductor device of claim 2 , wherein the V0 is present over the at least one first metal line away from the overlap area.

5. The semiconductor device of claim 1 , wherein the at least one first metal line is oriented orthogonal to the at least one second metal line.

6. The semiconductor device of claim 1 , wherein the oxygen diffusion blocking layer is absent from the top of the at least one first metal line away from the overlap area.

7. The semiconductor device of claim 1 , wherein the oxygen diffusion blocking layer comprises a material selected from the group consisting of: titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), and combinations thereof.

8. The semiconductor device of claim 1 , wherein the at least one first metal line and the at least one second metal line each comprises a contact metal selected from the group consisting of: copper (Cu), ruthenium (Ru), cobalt (Co), tungsten (W), and combinations thereof.

9. The semiconductor device of claim 1 , further comprising:
a liner present under and along sidewalls of the at least one first metal line.

10. The semiconductor device of claim 9 , wherein the liner comprises a material selected from the group consisting of: Ti, Ta, TiN, TaN, Ru, and combinations thereof.

11. The semiconductor device of claim 9 , wherein the oxygen diffusion blocking layer is present along the sidewalls of the at least one first metal line over the liner only in the overlap area.

12. A semiconductor device, comprising:
at least one first FET and at least one second FET;
at least one first metal line in contact with a source or drain of the at least one first FET;
at least one second metal line in contact with a gate of the at least one first FET, wherein the first metal line crosses the second metal line;
an oxygen diffusion blocking layer on top of the at least one first metal line in only an overlap area of the at least one first metal line and the at least one second metal line;
a first vertical interconnect (V0) present over the at least one first metal line and the oxygen diffusion blocking layer in the overlap area of the at least one first metal line and the at least one second metal line;
at least one third metal line in contact with a source or drain of the at least one second FET;
at least one fourth metal line in contact with a gate of the at least one second FET, wherein the third metal line crosses the fourth metal line; and
a second V0 present over the at least one third metal line away from an overlap area of the at least one third metal line and the at least one fourth metal line.

13. The semiconductor device of claim 12 , wherein the semiconductor device comprises a static random access memory (SRAM) device, the at least one first FET comprises at least one pull down (PD) transistor, and the at least one second FET comprises at least one pass gate (PG) transistor, and wherein the at least one PD transistor has a lower threshold voltage (Vt) than the at least one PG transistor.

Assignees

• IBM

Inventors

• Zhou Huimei
• Fan Su Chen
• Wang Miaomiao
• Liu Zuoguang

Classifications

• H10W20/037

  the barrier, adhesion or liner layers being on top of a main fill metal · CPC title

• H10W20/035

  combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H10W20/425 Primary

  Barrier, adhesion or liner layers · CPC title

• H10W20/0698 Primary

  Local interconnections · CPC title