Method of forming layout design

Patent metadata

Field	Value
Publication number	US-9336348-B2
Application number	US-201414484588-A
Country	US
Kind code	B2
Filing date	Sep 12, 2014
Priority date	Sep 12, 2014
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch.

First claim

What is claimed is:

1. A method of forming a layout design for fabricating an integrated circuit (IC), the method comprising:
identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design, the one or more areas corresponding to one or more regions of the IC subject to an electrical characteristic tuning process for fabricating the IC, the plurality of gate structure layout patterns extending along a first direction and having a predetermined pitch measurable along a second direction, and the predetermined pitch being smaller than a spatial resolution of a predetermined lithographic technology; and
generating a set of layout patterns overlapping the identified one or more areas, the set of layout patterns corresponding to one or more openings to be formed in a mask layer prior to performing the electrical characteristic tuning process, a first layout pattern of the set of layout patterns having a width measurable along the second direction, and the width of the first layout pattern being less than twice the predetermined pitch.

2. The method of claim 1 , wherein a second layout pattern of the set of layout patterns has a width measurable along the second direction, and the width of the second layout pattern being an integer multiple of the predetermined pitch.

3. The method of claim 1 , wherein the electrical characteristic tuning process is usable for leakage reduction of a dummy transistor of the IC or power adjustment of a functional transistor of the IC.

4. The method of claim 1 , wherein
the set of layout patterns comprises a second layout pattern;
the first layout pattern has an edge overlapping a cell boundary of the layout design; and
the second layout pattern has an edge overlapping the cell boundary of the layout design.

5. The method of claim 4 , wherein the edge of the first layout pattern and the edge of the second layout pattern abutting each other.

6. The method of claim 4 , wherein a first corner of the first layout pattern on the edge of the first layout pattern and a corner of the second layout pattern on the edge of the second layout pattern abutting each other.

7. The method of claim 6 , wherein
the set of layout patterns further comprises a third layout pattern;
the third layout pattern has an edge overlapping the cell boundary of the layout design; and
a second corner of the first layout pattern on the edge of the first layout pattern and a corner of the third layout pattern on the edge of the third layout pattern abutting each other.

8. The method of claim 1 , wherein the electrical characteristic tuning process comprises a threshold voltage tuning process or a gate structure trimming process.

9. A method of forming a layout design for fabricating an integrated circuit (IC), the method comprising:
identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design, the one or more areas corresponding to one or more regions of the IC subject to an electrical characteristic tuning process for fabricating the IC, the plurality of gate structure layout patterns extending along a first direction and having a predetermined pitch measurable along a second direction, and the predetermined pitch being smaller than a spatial resolution of a predetermined lithographic technology; and
generating a set of layout patterns overlapping the identified one or more areas, the set of layout patterns corresponding to one or more openings to be formed in a mask layer prior to performing the electrical characteristic tuning process, a first layout pattern and a second layout pattern of the set of layout patterns being separated by a first gap along the second direction, and a width of the first gap measurable along the second direction being less than twice the predetermined pitch.

10. The method of claim 9 , wherein the width of the first gap equals the predetermined pitch.

11. The method of claim 9 , wherein a third layout pattern and the first layout pattern of the set of layout patterns being separated by a second gap along the second direction, and a width of the second gap measurable along the second direction being an integer multiple of the predetermined pitch.

12. The method of claim 9 , wherein the first layout pattern has a width measurable along the second direction, and the width of the layout pattern is an integer multiple of the predetermined pitch.

13. The method of claim 9 , wherein the electrical characteristic tuning process is usable for leakage reduction of a dummy transistor of the IC or power adjustment of a functional transistor of the IC.

14. The method of claim 9 , wherein
the set of layout patterns comprises a third layout pattern;
the first layout pattern has an edge overlapping a cell boundary of the layout design; and
the third layout pattern has an edge overlapping the cell boundary of the layout design.

15. The method of claim 14 , wherein the edge of the first layout pattern and the edge of the third layout pattern abutting each other.

16. The method of claim 14 , wherein a first corner of the first layout pattern on the edge of the first layout pattern and a corner of the third layout pattern on the edge of the third layout pattern abutting each other.

17. The method of claim 16 , wherein
the set of layout patterns further comprises a fourth layout pattern;
the fourth layout pattern has an edge overlapping the cell boundary of the layout design; and
a second corner of the first layout pattern on the edge of the first layout pattern and a corner of the fourth layout pattern on the edge of the fourth layout pattern abutting each other.

18. The method of claim 9 , wherein the electrical characteristic tuning process comprises a threshold voltage tuning process or a gate structure trimming process.

19. A layout design for fabricating an integrated circuit (IC), comprising:
a first layout layer, comprising a plurality of gate structure layout patterns, the plurality of gate structure layout patterns extending along a first direction and having a predetermined pitch measurable along a second direction, and the predetermined pitch being smaller than a spatial resolution of a predetermined lithographic technology; and
a second layout layer, comprising a set of mask layout patterns arranged based on one or more opening regions, the one or more opening regions overlapping one or more of the plurality of gate structure layout patterns corresponding to one or more gate structures subject to an electrical characteristic tuning process, a first mask layout pattern of the set of mask layout patterns having a width measurable along the second direction, and the width of the first mask layout pattern being equal to the predetermined pitch.

20. The layout design of claim 19 , wherein a second mask layout pattern of the set of mask layout patterns has a width measurable along the second direction, and the width of the second layout pattern being an integer multiple of the predetermined pitch.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Hsieh Tung-Heng
• Lin Chung-Te
• Wang Sheng-Hsiung
• Zhuang hui-zhong
• Chiang Min-Hsiung
• Chiang Ting-Wei
• Tien Li-Chun

Classifications

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D84/907

  CMOS gate arrays · CPC title