Correlated electron resistive memory device and integration schemes

Patent metadata

Field	Value
Publication number	US-11690306-B2
Application number	US-202117407170-A
Country	US
Kind code	B2
Filing date	Aug 19, 2021
Priority date	Aug 19, 2021
Publication date	Jun 27, 2023
Grant date	Jun 27, 2023

Abstract

A resistive memory device is provided. The resistive memory device comprises a first metal oxide layer above a body electrode. A correlated electron layer located between a source and a drain and above the first metal oxide layer. A gate above a bottom portion of the correlated electron layer.

First claim

What is claimed:

1. A resistive memory device comprising:
a first metal oxide layer above a body electrode;
a correlated electron layer located between a source and a drain and above the first metal oxide layer; and
a gate above a bottom portion of the correlated electron layer.

2. The resistive memory device of claim 1 , further comprising:
a second metal oxide layer above the bottom portion of the correlated electron layer, wherein the second metal oxide layer separates the gate from the correlated electron layer.

3. The resistive memory device of claim 1 , wherein the source and the drain are over the first metal oxide layer.

4. The resistive memory device of claim 1 , wherein a length of the correlated electron layer between the source and the drain is longer than a thickness of the correlated electron layer.

5. The resistive memory device of claim 4 , wherein a length of the gate is shorter than the length of the correlated electron layer between the source and the drain.

6. The resistive memory device of claim 5 , wherein a length of the body electrode is at least equal to the length of the correlated electron layer between the source and the drain.

7. The resistive memory device of claim 2 , wherein the gate has a bottom surface, and the second metal oxide layer is arranged next to the bottom surface of the gate.

8. The resistive memory device of claim 7 , wherein the gate has side surfaces, and the second metal oxide layer is arranged next to the side surfaces of the gate.

9. The resistive memory device of claim 7 , wherein the gate has side surfaces, and spacer structures are arranged next to the side surfaces of the gate.

10. The resistive memory device of claim 4 , wherein a length of the gate is at least equal to the length of the correlated electron layer between the source and the drain.

11. The resistive memory device of claim 10 , wherein a length of the body electrode is at least equal to the length of the correlated electron layer between the source and the drain.

12. The resistive memory device of claim 10 , wherein the correlated electron layer partially overlaps a top surface of a lower portion of the source and a top surface of a lower portion of the drain.

13. The resistive memory device of claim 1 , wherein the first metal oxide layer is a transition metal oxide layer.

14. The resistive memory device of claim 2 , wherein
the second metal oxide layer is a transition metal oxide layer.

15. A resistive memory device comprising:
a first metal oxide layer above a body electrode;
a correlated electron layer having a bottom portion, wherein the bottom portion of the correlated electron layer is located at least partially between a source and a drain and above the first metal oxide layer;
a gate above the bottom portion of the correlated electron layer; and
the gate and the bottom portion of the correlated electron layer overlap the body electrode.

16. The resistive memory device of claim 15 , further comprising:
a second metal oxide layer above the bottom portion of the correlated electron layer, wherein the second metal oxide layer is between the gate and the correlated electron layer.

17. The resistive memory device of claim 15 , wherein the source and the drain are over the first metal oxide layer.

18. The resistive memory device of claim 17 , wherein the source and the drain partially overlap the body electrode.

19. A method of fabricating a resistive memory device, the method comprising:
forming a body electrode and a first metal oxide layer above the body electrode;
forming a source and a drain;
forming a correlated electron layer above the first metal oxide layer and between the source and the drain; and
forming a gate above a bottom portion of the correlated electron layer.

20. The method of claim 19 , wherein the formation of the source and the drain further comprises:
forming the source and the drain over the first metal oxide layer.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Hsieh Curtis Chun-I
• Hsu Wei-Hui
• Yi Wanbing
• Tan Juan Boon

Classifications

• H10N99/03 Primary

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