High electron mobility transistors having improved drain current drift and/or leakage current performance

Patent metadata

Field	Value
Publication number	US-10937873-B2
Application number	US-201916238853-A
Country	US
Kind code	B2
Filing date	Jan 3, 2019
Priority date	Jan 3, 2019
Publication date	Mar 2, 2021
Grant date	Mar 2, 2021

Abstract

A high electron mobility transistor includes a channel layer, a barrier layer on the channel layer, source and drain contacts on the barrier layer, a gate contact between the source and drain contacts, and a multi-layer passivation structure on the upper surface of the barrier layer between the source contact and the drain contact. The multi-layer passivation structure includes a first passivation layer that comprises a charge dissipation material directly contacts the upper surface of the barrier layer and a second passivation layer comprising a different material than the first passivation layer that also directly contacts the upper surface of the barrier layer. In some embodiments, at least one recess may be formed in the upper surface of the barrier layer and the second passivation layer may be formed within the recesses.

First claim

What is claimed is:

1. A high electron mobility transistor, comprising:
a channel layer;
a barrier layer on the channel layer, the barrier layer having a lower surface that is adjacent the channel layer and an upper surface that is opposite the lower surface;
a source contact on the upper surface of the barrier layer;
a drain contact on the upper surface of the barrier layer;
a gate contact on the upper surface of the barrier layer between the source contact and the drain contact; and
a passivation layer on the upper surface of the barrier layer between the source contact and the drain contact,
wherein a first recess and a second recess are provided in the upper surface of the barrier layer and extend further into the barrier layer than at least one of the source contact and the drain contact, and
wherein the passivation layer is within both the first recess and the second recess, and
wherein the first recess is adjacent the source contact and the second recess is adjacent the drain contact.

2. The high electron mobility transistor of claim 1 , wherein the passivation layer comprises a second passivation layer, the high electron mobility transistor further comprising a first passivation layer on the upper surface of the barrier layer between the source contact and the drain contact, wherein both the first passivation layer and the second passivation layer directly contact the barrier layer, and wherein the first passivation layer comprises a first material and the second passivation layer comprises a second material that is different than the first material.

3. The high electron mobility transistor of claim 2 , wherein the first material is a first silicon nitride material having a first ratio of silicon to nitrogen and the second material is a second silicon nitride material having a second ratio of silicon to nitrogen, wherein the first ratio of silicon to nitrogen is at least ten percentage points greater than the second ratio of silicon to nitrogen.

4. The high electron mobility transistor of claim 2 , wherein the first material is alumina and the second material is silicon nitride.

5. The high electron mobility transistor of claim 2 , further comprising a third recess in the upper surface of the barrier layer, wherein the second passivation layer is within the third recess, wherein the third recess is underneath the gate contact.

6. A high electron mobility transistor, comprising:
a channel layer;
a barrier layer on the channel layer, the barrier layer having a lower surface that is adjacent the channel layer and an upper surface that is opposite the lower surface;
a source contact on the upper surface of the barrier layer;
a drain contact on the upper surface of the barrier layer;
a gate contact on the upper surface of the barrier layer between the source contact and the drain contact;
a first passivation layer on the upper surface of the barrier layer between the source contact and the drain contact; and
a second passivation layer on the upper surface of the barrier layer between the source contact and the drain contact,
wherein a first recess is provided in the upper surface of the barrier layer, and the second passivation layer is within the first recess,
wherein both the first passivation layer and the second passivation layer directly contact the barrier layer, and
wherein the first recess is adjacent one of the source contact or the drain contact and only extends partially into the barrier layer.

7. The high electron mobility transistor of claim 6 , wherein the first passivation layer comprises a silicon-rich silicon nitride or alumina.

8. The high electron mobility transistor of claim 6 , wherein a portion of the first passivation layer that directly contacts the upper surface of the barrier layer is positioned between the gate contact and a portion of the second passivation layer that directly contacts the upper surface of the barrier layer.

9. The high electron mobility transistor of claim 6 , wherein the first passivation layer directly contacts the upper surface of the barrier layer for a first percentage of a distance between the source contact and the drain contact, the first passivation layer comprising a charge dissipation material, and the second passivation layer directly contacts the upper surface of the barrier layer for a second percentage of the distance between the source contact and the drain contact, the second passivation layer comprising a different material than the first passivation layer, and the second distance being smaller than the first distance.

10. A high electron mobility transistor, comprising:
a channel layer;
a barrier layer on the channel layer, the barrier layer having a lower surface that is adjacent the channel layer and an upper surface that is opposite the lower surface;
a source contact on the upper surface of the barrier layer;
a drain contact on the upper surface of the barrier layer;
a gate contact on the upper surface of the barrier layer between the source contact and the drain contact;
a first passivation layer that directly contacts the upper surface of the barrier layer between the source contact and the drain contact, the first passivation layer comprising a charge dissipation material; and
a second passivation layer that directly contacts the upper surface of the barrier layer between the source contact and the drain contact, wherein the second passivation layer comprises a different material than the first passivation layer,
wherein a first recess that has a depth that is less than a thickness of the barrier layer is provided in the barrier layer underneath the gate contact, and wherein the second passivation layer is in the first recess.

11. The high electron mobility transistor of claim 10 , wherein the first passivation layer comprises a charge dissipation material.

12. The high electron mobility transistor of claim 11 , further comprising a second recess in the upper surface of the barrier layer, and the second passivation layer is within the second recess.

13. A high electron mobility transistor, comprising:
a channel layer;
a barrier layer on the channel layer, the barrier layer having a lower surface that is adjacent the channel layer and an upper surface that is opposite the lower surface;
a source contact on the upper surface of the barrier layer;
a drain contact on the upper surface of the barrier layer;
a gate contact on the upper surface of the barrier layer between the source contact and the drain contact;
a first passivation layer that directly contacts the upper surface of the barrier layer between the source contact and the drain contact, the first passivation layer comprising a charge dissipation material, and
a second passivation layer that directly contacts the upper surface of the barrier layer between the source contact and the drain contact, the second passivation layer comprising a different material than the first passivation layer,
wherein a portion of the first passivation layer that directly contacts the upper surface of the barrier layer is positioned between the gate contact and a portion of the second passivation layer that directly contacts the upper surface of the barrier layer.

14. The high electron mobility transistor of claim 13 , wherein the second passivation layer is not a charge dissipation material.

15. The high electron mobility transistor of claim 13 , wherein the charge dissipation material is silicon-rich silicon nitride or alumina.

16. The high electron mobility transistor of claim 13 , wherein a first recess is provided in the upper surface of the b

Assignees

• Cree Inc

Inventors

• Lee Kyoung-Keun
• Radulescu Fabian
• Sheppard Scott

Classifications

• H10P50/646

  of Group III-V materials · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title

• H10P14/6329

  using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition · CPC title

• H10P14/3416

  Nitrides · CPC title